Sense Circuit Timing Control for NAND Flash Read Margin
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Solution Overview
Problem
The miniaturization of semiconductor memories, particularly NAND flash memory, has made it challenging to maintain operation reliability due to process variations, temperature fluctuations, and power supply voltage variations, which affect the on-current and off-leak current ratios, making it difficult to secure a sufficient read margin.
Innovation Solution
A semiconductor memory device configuration that includes a reference sense module formed on the same substrate as the sense module, generating a reference current based on the off-current flowing through unselected source lines, allowing for the same variations as the cell current, thereby compensating for fluctuations and improving read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor memory is miniaturized to increase storage density, then storage capacity is improved, but operation reliability deteriorates due to process variations and current ratio degradation
Solution Approach 1:
The patent creates a copy of the sense amplifier circuit as a reference sense amplifier that generates a reference current matching the cell current characteristics. This reference current copy compensates for variations in the actual sense amplifier by providing a matched reference for comparison, thereby maintaining read accuracy despite miniaturization-induced variations.
Solution Approach 2:
The patent dynamically adjusts the reference current magnitude to match the cell current characteristics under varying conditions (process, temperature, voltage). By changing the reference current parameter to track cell current variations, the system compensates for miniaturization effects and maintains sufficient read margin.
2Measurement precision
If sense amplifier current matching is improved to enhance read accuracy, then read margin is improved, but device complexity increases due to additional reference sense module
Solution Approach 1:
The patent merges the reference sense amplifier functionality with the existing sense amplifier structure, forming an integrated reference sense module. This consolidation achieves current matching for improved read accuracy while minimizing additional complexity by sharing common circuit elements and integrating into the existing memory block architecture.
3Quantity of substance
If three-dimensional stacked memory structure is adopted to increase storage density, then storage capacity is improved, but off-leak current accumulation increases affecting read margin
Solution Approach 1:
The reference sense amplifier creates a copy of the expected cell current including the off-leak current components. By comparing the actual cell current against this reference copy that includes accumulated off-leak characteristics, the system can accurately distinguish true data signals from off-leak current noise, maintaining read margin in 3D stacked structures.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, a bit line, a source line, and a sense circuit. The memory cell array includes memory strings which include memory cells connected in series and stacked above a semiconductor substrate. The bit line is coupled to one of the memory strings and is capable of transferring data. The source line is coupled to one of the memory strings. When data is read, a read current flows from a bit line into the source line. The sense circuit is coupled to the bit line and senses read data. An operation timing of the sense circuit is determined on the basis of a current flowing through the source line.