Vertical Memory Device Manufacturing Uniformity
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Solution Overview
Problem
The challenge in manufacturing vertical memory devices lies in forming semiconductor patterns uniformly, particularly in COP structures, where the selective epitaxial growth process using a polysilicon layer as a seed is not straightforward due to height distributions and the difficulty in connecting channels uniformly to the substrate.
Innovation Solution
A method involving the formation of a mold with alternately stacked insulation and sacrificial layers, where the first sacrificial layer includes nitride and is removed to form a gap, allowing for the formation of a channel connecting pattern without the need for an etch stop pattern, and the second sacrificial layer is replaced with a gate electrode, preventing C—N residue generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective epitaxial growth process is used to form semiconductor patterns, then channels can be formed on the substrate, but uniform distribution of semiconductor patterns is difficult to achieve due to height distributions
Solution Approach 1:
The patent divides the formation process into two distinct stages: first forming a uniform sacrificial layer pattern through self-aligned etching, then using this pattern as a template for semiconductor layer formation. This segmentation separates the pattern definition from the semiconductor growth, ensuring uniform distribution regardless of substrate height variations.
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary element that mediates between the substrate and the semiconductor layer. This sacrificial layer serves as a temporary structure that defines the pattern during fabrication, then is removed to create the final channel structure, avoiding direct dependence on substrate uniformity.
2Manufacturing precision
If etch stop pattern is added to protect sidewall during sacrificial layer removal, then selective removal is improved, but number of processes increases
Solution Approach 1:
The patent applies different etching selectivities to different layers by choosing materials with distinct chemical properties. The first sacrificial layer uses a material that is highly selective to the etchant used, allowing removal without affecting other layers, eliminating the need for additional protective etch stop patterns.
Solution Approach 2:
The patent creates a self-aligned pattern where the sacrificial layer pattern automatically defines the channel positions. This self-alignment copying mechanism ensures precise pattern transfer without requiring additional alignment steps or protective patterns, reducing process complexity.
3Manufacturing precision
If nitride is used in sacrificial layer, then etching selectivity is improved, but C—N residue is generated causing channel deterioration
Solution Approach 1:
The patent extracts the harmful C—N residue generation by removing nitride from the sacrificial layer composition. Instead, it uses oxide-based materials that do not produce carbon-nitrogen residues during etching, while maintaining sufficient etching selectivity through material selection and process optimization.
Solution Approach 2:
The patent changes the material parameter of the sacrificial layer from nitride-based to oxide-based materials. This parameter change eliminates the C—N residue issue while maintaining etching selectivity through the use of materials like silicon oxide or germanium oxide that have appropriate etching characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process by ensuring uniform channel formation and prevents deterioration of channel characteristics, reducing the number of processes required and avoiding C—N residue issues.
Implementation Method 1
The first sacrificial layer may be removed through the opening to form a first gap
Implementation Method 2
the second sacrificial layer may be replaced with a gate electrode. Particularly, when the gate electrode is formed by removing the second sacrificial layer, the second sacrificial layer may not include a nitride, and thus a C—N residue may not be generated during the removal of the second sacrificial layer
Data Source
AI summary
In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.