SiGe FinFET Ge Diffusion Control via Segmented Epitaxy
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Solution Overview
Problem
The formation of SiGe fins for FinFET devices is challenging due to germanium diffusion issues, which affect the performance of adjacent n-channel devices, and existing fabrication techniques result in non-uniform fin shapes and limited thermal budgets.
Innovation Solution
A method involving a substrate with alternating regions for Si and SiGe fin formation, where Si fins are defined first, followed by converting them into wider SiGe fins and laterally reducing their width to form separate fin structures for p-channel and n-channel FinFET transistors, using directional etching and epitaxial growth to control Ge diffusion and achieve uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive thermal budget is used for SiGe fabrication, then SiGe fins can be formed, but germanium diffuses into adjacent substrate regions affecting n-channel device performance
Solution Approach 1:
The substrate is divided into alternating first and second regions, with fins formed in both regions. SiGe material is selectively grown only in the first regions (p-channel device regions) while second regions (n-channel device regions) remain as pure silicon, preventing Ge diffusion into n-channel devices
Solution Approach 2:
Different material compositions are used in different regions: SiGe material (with germanium) is used in first regions for p-channel devices where high performance is needed, while second regions use pure silicon to avoid Ge diffusion issues, giving each region the optimal material properties for its function
2Object-affected harmful factors
If SiGe fins are formed after Si fins are defined, then Ge diffusion into n-channel regions is avoided, but fin shape uniformity deteriorates
Solution Approach 1:
Fins are pre-defined in both first and second regions using directional etching before SiGe material growth. This preliminary fin formation in both regions ensures uniform fin shapes, and subsequent selective SiGe growth in only the first regions maintains this uniformity while avoiding Ge diffusion into second regions
3Reliability
If SiGe material is used for p-channel FinFET devices, then transistor performance is improved, but fabrication complexity increases due to thermal budget constraints
Solution Approach 1:
The fabrication process is segmented into distinct steps: (1) forming fins in both regions, (2) selectively growing SiGe material only in first regions, (3) laterally reducing SiGe fin width in first regions. This segmentation allows controlled use of SiGe material to improve p-channel device performance while managing fabrication complexity through systematic process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes Ge diffusion, ensures uniform fin shapes, and enhances transistor performance by allowing for precise control over fin dimensions and material composition, addressing the limitations of prior art techniques.
Implementation Method 1
converting the fins in the second region made of said first semiconductor material into converted fins made of a second semiconductor material
Implementation Method 2
laterally reducing a width of the converted fins made of the second semiconductor material
Implementation Method 3
These thermal treatments can cause germanium to diffuse from the substrate regions where p-channel devices are being fabricated
Data Source
AI summary
A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type.