Semiconductor Device Conductive Layer Impurity Diffusion Control

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Solution Overview

Problem

Current three-dimensionally integrated semiconductor devices face challenges in improving writing speed due to the diffusion of impurities from conductive layers to insulating layers, which slows down the application of threshold voltage and affects data writing efficiency.

Innovation Solution

Incorporating specific elements like carbon, nitrogen, and germanium in designated portions of the conductive layers to suppress the diffusion of impurities, thereby reducing the expansion of depleted regions and enhancing writing speed by using a layered structure with distinct impurity distributions within the conductive layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional conductive layers are used without specific element incorporation, then manufacturing is simpler, but impurity diffusion occurs from conductive layers to insulating layers, slowing down threshold voltage application and reducing writing speed

Engineering Contradiction:
Improvewriting speedVSAvoidconductive layer structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The conductive layer is divided into multiple portions (first, second, and third portions) with different impurity concentrations and compositions. The first and second portions contain high concentrations of first element (boron or phosphorus) for conductivity, while the third portion contains second element (carbon, nitrogen, oxygen, or germanium) to suppress impurity diffusion. This local differentiation allows the conductive layer to simultaneously provide electrical conductivity and prevent diffusion, resolving the contradiction between writing speed improvement and structural complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The conductive layer is formed as a composite structure containing multiple elements (first element for conductivity, second element for diffusion suppression) distributed in different portions. This composite approach enables the single conductive layer to perform dual functions: maintaining electrical conductivity through first element while preventing impurity diffusion through second element, thereby improving writing speed without requiring multiple separate layers.

Inventive Principle:
Principle #40Composite materials

2Productivity

If impurity diffusion is allowed to occur, then manufacturing process is simpler, but depleted regions expand, slowing down threshold voltage application and reducing data writing efficiency

Engineering Contradiction:
Improvedata writing efficiencyVSAvoidimpurity distribution control
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Different portions of the conductive layer are assigned different impurity characteristics: the first and second portions have high first element concentration for conductivity, while the third portion has second element concentration specifically engineered to suppress diffusion. This localized quality control prevents depleted region expansion in critical areas, maintaining fast threshold voltage application and high data writing efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The second element (carbon, nitrogen, oxygen, or germanium) is incorporated into the third portion of the conductive layer in advance to create a diffusion barrier before impurity diffusion can occur. This preliminary anti-action prevents the expansion of depleted regions, ensuring that threshold voltage can be applied quickly and data writing efficiency remains high.

Inventive Principle:
Principle #9Preliminary anti-action

3Speed

If uniform impurity distribution is used in conductive layers, then manufacturing is easier, but impurity diffusion to insulating layers occurs, affecting writing speed

Engineering Contradiction:
Improvewriting speedVSAvoidimpurity distribution control
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

Instead of uniform impurity distribution, the conductive layer is designed with non-uniform impurity distribution where the third portion contains second element (carbon, nitrogen, oxygen, or germanium) specifically to suppress diffusion to insulating layers. This local quality differentiation, while more complex to manufacture, enables faster writing speed by preventing impurity diffusion that would otherwise slow down threshold voltage application.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The impurity concentration and composition parameters are changed across different portions of the conductive layer. The first and second portions maintain high first element concentration for conductivity, while the third portion is modified by adding second element to change its diffusion characteristics. This parameter variation enables the conductive layer to suppress impurity diffusion and improve writing speed.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively improves writing speed in memory layers by preventing impurity diffusion, allowing for faster data storage and retrieval, particularly when boron or phosphorus is used as the first element and carbon is included in the third portion to suppress their diffusion.

Implementation Method 1

the diffusion of impurities from conductive layers to insulating layers

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

Incorporating specific elements like carbon, nitrogen, and germanium in designated portions of the conductive layers to suppress the diffusion of impurities

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS9437601B1Semiconductor device
Publication Date: 2016.09.06 KIOXIA CORP
  • US9437601B1 patent drawing
  • US9437601B1 patent drawing
  • US9437601B1 patent drawing

AI summary

A semiconductor device according to an embodiment includes a stacked body, and a semiconductor pillar. The stacked body includes first insulating layers and conductive layers. The conductive layer includes silicon. At least one of the conductive layers includes a first portion, a second portion, and a third portion. The first portion includes a first element selected from at least one of boron and phosphorus. The second portion includes the first element. The third portion is provided between the first portion and the second portion in a stacking direction of the conductive layers and the first insulating layers. The third portion includes a second element. The second element is selected from at least one of carbon, nitrogen, oxygen, and germanium. The semiconductor pillar pierces through the stacked body. The semiconductor pillar extends in the stacking direction.