Vertical Non-Volatile Memory Device Charge Storage Segmentation
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Solution Overview
Problem
Current non-volatile memory devices face challenges in enhancing integration and charge storage characteristics, particularly when cell transistors are stacked vertically, as they struggle to maintain effective data retention and separation between transistors.
Innovation Solution
The proposed vertical non-volatile memory device incorporates a stack body with gate patterns and interlayer insulating patterns alternately stacked, featuring through holes, recess holes, and semiconductor pillars, along with charge storage layers and dummy charge storage layers, which improve data storage and retention by separating and insulating charge storage layers from dummy layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cell transistors are stacked vertically to improve integration, then device integration is enhanced, but charge storage characteristics and data retention deteriorate
Solution Approach 1:
The memory device is divided into multiple stacked cell transistors, each with separate charge storage layers. This segmentation allows independent charge storage in each transistor while maintaining vertical integration, resolving the contradiction between high integration and charge storage effectiveness.
Solution Approach 2:
Dummy charge storage layers are introduced as intermediary structures between real charge storage layers. These dummy layers act as mediators to enhance charge confinement and prevent charge leakage between adjacent transistors, thereby improving charge storage characteristics while maintaining vertical stacking.
2Productivity
If cell transistors are stacked vertically, then integration increases, but separation between transistors becomes difficult
Solution Approach 1:
Each cell transistor is segmented with dedicated charge storage layers and isolated by dummy charge storage layers. This segmentation provides clear electrical separation between vertically stacked transistors, making it easier to control and distinguish individual transistor operations despite their close proximity.
Solution Approach 2:
The dummy charge storage layers are strategically placed only in specific regions where transistor separation is needed, while maintaining charge storage functionality in active regions. This local modification achieves transistor separation without compromising overall integration density.
3Productivity
If charge storage layers are placed close together for high integration, then device density improves, but charge retention and isolation worsen
Solution Approach 1:
Dummy charge storage layers serve as intermediary barriers between real charge storage layers. These intermediary structures prevent direct charge interaction and leakage between adjacent transistors, ensuring reliable charge retention even when transistors are densely packed in vertical stacks.
Solution Approach 2:
The charge storage structure uses composite arrangements of real charge storage layers and dummy charge storage layers. This composite structure combines the charge storage function of real layers with the isolation function of dummy layers, achieving both high density and reliable charge retention.
Data Source
AI summary
A vertical non-volatile memory device includes a stack body including gate patterns and interlayer insulating patterns stacked in a stacking direction, the stack body having a through hole, which extends in the stacking direction, in the gate patterns and in the interlayer insulating patterns; a semiconductor pillar in the through hole and extending in the stacking direction; data storage structures between the gate patterns and the semiconductor pillar in the through hole, the data storage structures including charge storage layers; and dummy charge storage layers on a sidewall of the interlayer insulating patterns toward the semiconductor pillar in the through hole.