Embedded Flash Gate Stack With Recessed Floating Gate Integration
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Solution Overview
Problem
The integration of embedded flash memory devices with other types of circuits on a semiconductor chip faces challenges due to structural differences, particularly in forming charge storage layers and gate stacks, which affects process complexity and threshold voltage matching.
Innovation Solution
The method involves forming charge storage layers and gate stacks with a bottom dielectric layer extending into a recess in the semiconductor substrate, embedding a majority of the charge storage layer within the substrate, and using a dual layer blocking structure with a high-k dielectric and top dielectric layer to reduce gate stack height and maintain charge retention, while forming metal gates to match threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory devices are integrated with other circuits on the same chip, then System-On-Chip functionality is achieved, but process complexity increases due to structural differences
Solution Approach 1:
The flash memory structure is segmented into distinct functional regions: a recess region containing the charge storage layer and tunnel dielectric, and a planar region with conventional transistor structures. This segmentation allows each region to be optimized independently while maintaining overall integration, reducing process complexity through modular design
Solution Approach 2:
Different structural configurations are applied to different regions of the chip: the recess region uses a vertical stacked structure with charge storage layer for flash memory functionality, while surrounding regions use planar structures for conventional circuits. This local differentiation enables co-integration of diverse circuit types with optimized performance for each function
2Reliability
If charge storage layers are formed over the substrate surface, then flash memory functionality is achieved, but gate stack height increases affecting CMP processes
Solution Approach 1:
The charge storage layer is positioned in a vertical recess rather than extending horizontally over the substrate surface. This dimensional change from a planar to a vertical configuration reduces the horizontal gate stack height while maintaining the charge storage functionality through the vertical tunnel dielectric and charge storage layer structure
Solution Approach 2:
The charge storage layer and tunnel dielectric are nested within a recess in the substrate, creating a compact vertical structure. This nesting approach embeds the flash memory charge storage components within the substrate volume rather than adding height above the surface, facilitating subsequent CMP processes
3Adaptability or versatility
If different circuit structures are used for flash memory and other circuits, then functional integration is achieved, but threshold voltage matching becomes difficult
Solution Approach 1:
The gate stack structures in both recess and planar regions use identical materials and doping configurations, ensuring consistent threshold voltage characteristics. Only the geometric configuration differs (vertical vs. planar), allowing threshold voltage matching while maintaining functional differentiation for flash memory and conventional circuits
Data Source
AI summary
An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.