Embedded Flash Cell Layout With Shared Source-Drain Pitch Reduction
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Solution Overview
Problem
Current flash memory technologies face challenges in achieving high integration and compact size due to limitations in reducing the pitch of cell layout in the row direction.
Innovation Solution
An embedded flash memory cell array structure that shares the source or drain of transistors with adjacent control gate transistors, arranged in a zigzag manner to reduce the row direction length and improve integration by overlapping selection transistors in the column direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pitch of cell layout in the row direction is reduced to improve integration, then the device complexity increases due to shared source and drain regions
Solution Approach 1:
Adjacent control gate transistors share common source and drain regions, merging previously separate structures into unified regions. This reduces the overall cell pitch in the row direction while maintaining transistor functionality, directly resolving the contradiction between reduced cell area and increased layout complexity.
Solution Approach 2:
The shared source and drain regions serve multiple adjacent transistors simultaneously, making these regions multi-functional. A single source/drain region acts as both the source for one transistor and the drain for another, reducing the total number of discrete regions needed and thereby reducing cell area.
2Area of stationary object
If selection transistors are arranged to overlap in the column direction to reduce cell area, then the manufacturing precision requirements increase
Solution Approach 1:
Selection transistors are arranged to overlap in the column direction rather than being strictly adjacent in the row direction. This dimensional reorganization allows area reduction by utilizing vertical space more efficiently, while the overlapping arrangement can be implemented through standard multi-patterning techniques to manage manufacturing precision requirements.
Data Source
AI summary
The present invention discloses an embedded flash memory cell array structure characterized by improving integration by reducing the pitch of the cell layout in the row direction by sharing a source or drain with an adjacent control gate transistor.