Embedded Flip Chip Substrate Layout to Prevent Warping
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Solution Overview
Problem
Existing flip chip packaging methods require lengthy processes and high costs due to the need for cavity formation, laser drilling, and electroplating, and result in substrate warping from asymmetric stress during curing.
Innovation Solution
An embedded flip chip package substrate method that eliminates cavity formation and laser drilling, using reflow soldering for electrical connection and symmetrical dielectric layers to balance thermal stress, reducing manufacturing steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cavity formation, laser drilling, and electroplating are used for embedding flip chip, then electrical connection between chip and substrate is achieved, but manufacturing process becomes lengthy and costly
Solution Approach 1:
The patent extracts and eliminates the cavity formation step from the traditional embedding process. By directly mounting the flip chip onto the substrate surface and using wire bonding for electrical connection, the method removes the need for creating cavities, laser drilling, and electroplating, thereby significantly shortening the manufacturing process while maintaining reliable electrical connection.
2Ease of manufacture
If single-sided encapsulation is used for chip packaging, then packaging is simplified, but substrate warping occurs due to asymmetric stress during curing
Solution Approach 1:
The patent applies asymmetry principle by using single-sided encapsulation with a specific structural design. The encapsulant is applied only on one side of the substrate, but the substrate itself is designed with compensatory features that balance the thermal stress during curing, preventing warping while maintaining manufacturing simplicity.
3Reliability
If traditional embedding method with cavity and multiple processing steps is used, then chip can be embedded in substrate, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the chip mounting and electrical connection steps into a more integrated process. By mounting the flip chip directly on the substrate surface and using wire bonding for interconnection, the method combines multiple traditional steps (cavity formation, chip embedding, electrical connection) into a simplified sequence, reducing manufacturing complexity while ensuring reliable chip embedding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method shortens the process flow, reduces manufacturing complexity, and prevents substrate warping by ensuring equal thermal expansion across the substrate surfaces, thus enhancing manufacturing efficiency and reducing costs.
Implementation Method 1
curing the packaging layer
Implementation Method 2
by using reflow soldering to solder the chip to the first line layer
Implementation Method 3
by using reflow soldering to solder the chip to the first line layer, the electrical interconnection between the chip and the first line layer can be conveniently realized
Implementation Method 4
symmetrical dielectric layers to balance thermal stress, reducing manufacturing steps and costs
Data Source
AI summary
A manufacturing method for an embedded flip chip package substrate includes laminating a first dielectric layer on the first line layer formed on a carrier plate, forming a first window on the first dielectric layer, filling a first copper post in the first window, forming a second window on the first dielectric layer, mounting a flip chip to the second window, sequentially stacking a packaging layer and a second dielectric layer covered with a first metal layer on the first dielectric layer, pressing a packaging layer encapsulating the first copper post and the flip chip and a second dielectric layer, curing the packaging layer, opening a hole through the first metal layer, the second dielectric layer and the packaging layer to form an interlayer conducting blind hole, forming a second line layer on the first metal layer, and removing the carrier plate to obtain a package substrate.