Embedded Gate Interconnects in Vertical IGBT Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IGBT structures face challenges in achieving low on-voltage and high switching speed while maintaining reliability, especially under high-voltage and large-current conditions, with concerns about electrical insulation reliability and potential degradation of insulating films during long-term high-temperature operations.
Innovation Solution
The semiconductor device incorporates a vertical IGBT structure with a trench gate structure, where gate electrodes and interconnects are formed within the semiconductor layer, using insulating films and polycrystalline silicon, and are designed to be orthogonal to each other, avoiding surface metal gate interconnects to enhance insulation reliability and reduce capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If surface metal gate interconnects are used, then electrical connection is simplified, but insulation reliability deteriorates and capacitive coupling increases
Solution Approach 1:
The patent extracts the gate interconnect from the surface level and embeds it within the semiconductor layer. The gate interconnect is formed inside a trench structure at the same depth as the gate electrode, eliminating surface metal interconnects and their associated insulation and capacitive coupling problems while maintaining electrical connectivity through the embedded configuration
Solution Approach 2:
The patent transitions the gate interconnect from a surface-level two-dimensional layout to a three-dimensional embedded structure within the semiconductor layer. By positioning the gate interconnect vertically within the trench at the same depth as the gate electrode, the design utilizes the depth dimension to achieve both insulation and electrical connection objectives
2Reliability
If insulating films are used for gate electrode insulation, then electrical insulation is achieved, but insulating film degradation occurs during long-term high-temperature operations
Solution Approach 1:
The patent replaces the insulating film with a semiconductor layer-based insulation structure. The gate electrode and gate interconnect are both embedded within the semiconductor layer, utilizing the intrinsic electrical properties of the semiconductor material for insulation rather than relying on separate insulating films that degrade at high temperatures
Solution Approach 2:
The patent employs the semiconductor layer itself as both the structural matrix and the insulating medium. The embedded gate electrode and gate interconnect are surrounded by the semiconductor layer, which provides electrical insulation through its material properties rather than requiring an additional insulating film layer
3Reliability
If gate electrodes and gate interconnects are formed with complex layout, then electrical connection is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the gate electrode and gate interconnect into a unified embedded structure within the same trench. Both elements are formed at the same depth within the semiconductor layer, sharing the same fabrication process steps and depth control parameters, which simplifies manufacturing precision requirements while maintaining effective electrical connection
Solution Approach 2:
The patent positions the gate interconnect at the same depth as the gate electrode, creating an equipotential arrangement where both elements experience similar electrical and physical conditions. This uniform positioning simplifies the manufacturing process by requiring consistent trench depth control rather than precise differential depth control
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer provided between the first electrode and the second electrode, a plurality of gate electrodes provided in the semiconductor layer and extending in a first direction, a plurality of gate interconnects provided in the semiconductor layer and connected with the gate electrodes, the gate interconnects extending in a second direction crossing the first direction, an insulating film provided between the gate electrodes and the semiconductor layer, and between the gate interconnects and the semiconductor layer, and an inter-layer insulating film provided between the gate electrodes and the second electrode, and between the gate interconnects and the second electrode.