Embedded Gate Structure for MOSFET Short-Channel Effects
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Solution Overview
Problem
The scaling of MOSFET channel length leads to significant short-channel effects, such as reduced threshold voltage, increased power consumption, and reduced carrier mobility, which are challenging to control in traditional semiconductor devices, especially in fully depleted devices where achieving thin channel silicon layers is difficult and costly.
Innovation Solution
A semiconductor device with a second gate embedded partially in the substrate, featuring a floating gate and control gate with dielectric layers, and source/drain regions formed on a semiconductor assistant substrate, which increases the distance between gates and source/drain regions, reducing parasitic capacitances and resistances, and enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of MOSFETs is scaled down to improve device integration and performance, then device density and switching speed are improved, but short-channel effects become significant causing threshold voltage reduction, increased power consumption, and reduced carrier mobility
Solution Approach 1:
The patent introduces a second gate embedded in the substrate beneath the channel region, transitioning from a traditional single-planar gate structure to a three-dimensional configuration. This vertical dimension allows the second gate to control the channel from below, providing additional electrostatic control over the depleted channel region and effectively suppressing short-channel effects while maintaining scaled dimensions.
Solution Approach 2:
The gate control function is segmented into two independent gates: a first gate on the surface and a second gate embedded in the substrate. Each gate can be independently controlled, allowing separate optimization of different functions - the surface gate for primary switching and the embedded gate for threshold voltage control and short-channel effect suppression.
2Reliability
If more impurity elements are doped into the channel to control short-channel effects, then threshold voltage control is improved, but carrier mobility in the channel is reduced
Solution Approach 1:
The patent extracts the threshold voltage control function from impurity doping and transfers it to the second embedded gate. By using the embedded gate to control the channel depletion, the need for heavy impurity doping is eliminated, thereby maintaining high carrier mobility while achieving effective threshold voltage control through electrostatic means.
3Reliability
If the thickness of the channel silicon layer is reduced to achieve fully depleted device structure, then short-channel effects are mitigated, but manufacturing difficulty and cost increase significantly
Solution Approach 1:
The patent creates a locally depleted channel region through the embedded second gate rather than requiring uniform thinning of the entire channel layer. This allows the channel to be selectively depleted only where needed for device operation, achieving fully depleted characteristics without the manufacturing challenges of controlling ultra-thin channel layers across the entire wafer.
4Reliability
If source and drain region edges are expanded to reduce their resistances, then source/drain resistance is reduced, but parasitic capacitances between source/drain regions and gates increase
Solution Approach 1:
The embedded second gate structure creates a virtual extension of the gate control into the source/drain regions. This virtual gate structure provides electrostatic control over the expanded source/drain edges, allowing them to be enlarged for lower resistance while the embedded gate suppresses the resulting parasitic capacitances through field effect control.
Data Source
AI summary
A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate that is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of the source and drain regions, and parasitic capacitances.