Nanoinformatics TRIZ Cases

Aligning barrier dopant levels with quantum well valence edges enables real space hole transfer.

A thin film transistor semiconducting layer incorporates enriched metallic carbon nanotubes to boost charge carrier mobility.

A block copolymer treatment method uses phase separation to form precise circular patterns on semiconductor substrates.

A carbon nanotube thin film transistor with a sub-2nm semiconducting layer eliminates metallic tube leakage, raising the on/off current ratio.

A carbon-based storage element paired with a diode steering element enables multi-state data retention, reducing leakage current and fabrication complexity.

Transferring a super-aligned carbon nanotube film onto an insulating substrate eliminates solvent dispersion issues and prevents aggregation.

A laterally porous film structure with interpenetrating functional materials enhances charge transport in opto-electronic devices.

Chemical mechanical polishing planarizes the second gate layer against a hard mask, reducing masking steps for logic integration.

Vacuum-deformed elastomeric stamps deposit patterned metal layers on non-planar substrates without damaging fragile coatings.

A micro-conformal template uses a segmented backing and nanopatterned layer to maintain feature fidelity during imprinting.

A buried boron nitride layer suspends semiconductor nanowires above a substrate to maintain precise vertical positioning.

A transistor modifies channel bandwidth via gate voltage to achieve high ON/OFF ratios.

Computational modeling guides carbon nanotube template editing to overcome silicon lithography limitations and form complex circuits.

Carbon nanotube composites with nanoscopic particles enable controlled density and thick films in one spin coat step, eliminating multiple processing stages.

A control system adjusts operational parameters for optical media production using real-time feedback from embossing and coating processes.

Vertical carbon nanotube emitters focus electrons onto phosphor pixels, reducing voltage requirements while maintaining high resolution.

Co-integrates standard-gate and extended-gate nanosheet transistors on a shared substrate using optimized sacrificial layer thicknesses.

Intertwined spin injector and light generator regions eliminate interface defects to boost external efficiency in spin-sensitive UV LEDs.

An embedded second gate controls the channel from below, suppressing short-channel effects while maintaining high carrier mobility.

Carbon nanotubes mixed with organic semiconductors boost charge mobility above 3.3 cm2/V·sec, resolving low-speed limitations in flexible displays.

A solid electrolyte stamp patterns a conductive film to define recessed features on a semiconductor substrate.

Atomic layer deposition coats colloidal quantum dots with inorganic aluminum oxide to enhance electronic coupling and photoconductivity.

An isolation pedestal electrically separates the semiconductor body from the substrate to suppress sub-fin leakage currents in tri-gate transistors.

Metalized pattern-trenched flip-chip removes spurious microwave modes without dielectric loss.

Composite grating alignment radiation detects template substrate offset, resolving lithography misalignment.

A magnetic tunnel junction transistor switches magnetization orientation via gate voltage to modulate source-drain resistance.

Template imprinting patterns for FinFETs and planar devices eliminates multiple resist layers, reducing process complexity and noise sensitivity.

Recessing inner gate spacers exposes channel tip regions to clad source and drain regions, inducing uniaxial strain.

Photochemical synthesis of sp3 defects in single-walled carbon nanotubes using halogen precursors overcomes random defect formation and low conductance.

A vacuum tunneling device uses gradient deposition to form a sealing layer that fills the upper portion of an insulating interlayer opening.

Replacing metal electrodes with carbon nanotubes resolves thermal stability limits, enabling reliable operation in extreme environments.

Ohmic-contact-gated carbon nanotube transistors use self-aligned dielectric extensions to define device channels.

Chlorine plasma treatment modifies platinum nano-crystals to enable selective wet etching without damaging the underlying tunnel oxide layer.

Wrap-around magnetic side shields in a scissor read head prevent magnetization flipping, reducing effective track width and improving data density.

Digital spatial modulator moves with sub-pixel steps to generate precise curing patterns, overcoming 65 μm pixel pitch limits that cause extrusion formation.

Sliding outer shells of multiwalled nanotubes reversibly tune thermal conductance, resolving the trade-off between stable conduction and variable control.

An etch stop-electric well layer forms a barrier during sacrificial layer removal in gate-all-around nanowire transistors.

Replacing sacrificial material in vertical TFET nanowires with heterojunctions improves on-currents by resolving low tunneling efficiency in silicon devices.

A semiconductor device featuring a suspended silicon channel surrounded by a gate structure and dielectric layer.

Segmented nozzles direct clean gas to form airflow that reduces particle attachment, avoiding the need to enlarge the air conditioning system.

Patterned adhesion promoters on a carrier film transfer fixable material to create precise alignment layers, eliminating expensive mask alignment steps.

Suspended nanowires overcome electrical impedance limits by converting mechanical vibration directly into detectable current signals.

Thick germanium nitride passivation reduces interfacial states and improves thermal stability in germanium nanowire devices.

Doping the electron transport layer with C60 and organic n-type impurities lowers driving voltage while maintaining high brightness in large displays.

A carbon nanotube device with quantum dot radiation molecules emits electromagnetic radiation through electron-hole recombination.

Adhesive layers define reference points for self-aligned trenches, reducing parasitic capacitance while lowering manufacturing complexity.

Synchronizing pulsed light emission with substrate stage drive timing eliminates exposure non-uniformity caused by plasma generation delays at scan boundaries.

MIEC layers with conductive defect dopants form access diodes that deliver high current densities and ultra-low leakage.

Electroplating nanowires in solid masks controls diameter variation and enables CMOS-compatible vertical FET fabrication.