Split Gate Memory Cell Manufacturing via CMP Planarization
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Solution Overview
Problem
The manufacturing of split gate non-volatile memories (NVMs) is hindered by the close proximity of two gates separated by a charge storage layer, which complicates processing, and the integration with logic transistors increases the number of process steps, necessitating an improvement in manufacturing efficiency.
Innovation Solution
A method involving the formation of a first gate material layer over a gate dielectric, a hard mask layer, and a charge storage layer with nanocrystals, followed by a second thicker gate material layer that is polished to be even with the hard mask, allowing for simultaneous patterning of select, control, and logic gates, with subsequent etching and spacer formation to define bitcells and logic transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a split gate structure with two gates separated by a charge storage layer is used, then non-volatile memory functionality is achieved, but manufacturing complexity increases due to the close proximity of the two gates
Solution Approach 1:
The gate structure is segmented into two separate gate layers (first gate material layer and second gate material layer) that can be independently formed and patterned. This segmentation allows each gate to be processed separately, reducing the manufacturing complexity associated with forming two gates in close proximity while maintaining the split gate functionality for non-volatile memory operation.
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional stacked gate structure where the first and second gate material layers are vertically stacked with the charge storage layer in between. This dimensional change allows the two gates to be separated in the vertical dimension rather than being constrained in close horizontal proximity, thereby reducing manufacturing complexity while preserving the split gate functionality.
2Adaptability or versatility
If NVM is integrated with logic transistors, then system functionality is improved, but the number of process steps increases
Solution Approach 1:
The patent employs a common gate dielectric layer and shared processing steps for both the NVM cell transistors and the logic transistors. The gate dielectric layer serves both memory and logic functions, and the same semiconductor substrate and basic transistor formation processes are used for both device types. This multi-functionality approach allows NVM and logic to be integrated while minimizing the increase in process steps.
Solution Approach 2:
The patent merges the formation processes of NVM and logic transistors by using common layers (such as the gate dielectric layer 16 and substrate 12) and shared processing steps. The first and second gate material layers are formed using similar deposition and patterning processes that would also be used for logic transistor gates, thereby combining the manufacturing flows and reducing the total number of unique process steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by reducing the number of masking steps and enables efficient formation of bitcells and logic transistors, improving the reliability and efficiency of split gate NVMs.
Implementation Method 1
a charge storage layer with nanocrystals
Implementation Method 2
An etch back, preferably performed by chemical mechanical polishing (CMP), results in the second layer being even with a top surface of the remaining hard mask material.
Data Source
AI summary
A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.