Vertical Nanowire FETs via Electroplated Templates
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Solution Overview
Problem
Existing methods for fabricating vertical Field Effect Transistor (FET) devices using semiconductor nanowires face challenges in controllability and integration due to the variability in nanowire diameter and the limitations of using wide band-gap compound semiconductors like CuSCN, which restricts channel geometry and device applications.
Innovation Solution
The method involves electroplating semiconductor nanowires within predetermined templates with deep columnar pores, allowing for precise control over nanowire diameter and integration, using a process compatible with Complementary Metal Oxide Semiconductor (CMOS) technology, to form vertically oriented FETs with improved controllability and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CVD process is used to grow nanowires from catalytic particles, then nanowire vertical devices can be fabricated, but the catalytic particles agglomerate in liquid form causing variation in nanowire diameter and poor device performance controllability
Solution Approach 1:
The patent applies preliminary action by pre-forming a solid mask layer with predetermined patterns before nanowire growth. This mask layer defines the exact locations and dimensions of nanowire formation sites, preventing catalytic particle agglomeration and ensuring uniform nanowire diameter. The mask is prepared in advance to control the growth process, rather than relying on liquid catalytic particles that aggregate during growth.
Solution Approach 2:
The patent introduces a solid mask layer as an intermediary between the substrate and the nanowire growth process. This mask layer acts as a template that mediates the formation of nanowires, controlling their position, size, and distribution. The mask layer transfers the desired nanowire pattern from the design to the actual structure, eliminating the need for liquid catalytic particles.
2Adaptability or versatility
If wide band-gap compound semiconductor CuSCN is used for nanowire fabrication, then vertical nanowire structures can be formed, but the channel geometry options and device application versatility are restricted
Solution Approach 1:
The patent applies parameter changes by varying the material composition of the mask layer to control nanowire properties. By changing the mask material composition and deposition parameters, different nanowire materials and geometries can be achieved. This allows transition from fixed CuSCN nanowires to versatile nanowire structures with controlled composition, shape, and size suitable for various device applications.
Solution Approach 2:
The patent achieves universality by creating a general fabrication platform using the mask layer approach that can produce nanowires from various materials, not limited to CuSCN. The same mask-based methodology can be applied to grow nanowires of different semiconductors, metals, and compounds, enabling diverse channel geometries and device applications while maintaining a consistent manufacturing process.
3Productivity
If traditional scaling down of device dimensions is used to improve FET performance, then circuit performance can be enhanced, but fundamental scaling limits are reached
Solution Approach 1:
The patent applies dimensionality change by transitioning from traditional planar (2D) FET scaling to vertical (3D) nanowire FET structures. Instead of continuing to scale down horizontal dimensions which face fundamental limits, the invention grows nanowires vertically from the substrate, adding a vertical dimension to the device architecture. This enables continued performance improvement without further horizontal scaling by exploiting the vertical growth direction and three-dimensional device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of vertically oriented FETs with electroplated nanowires of mid or low band-gap semiconductors, enhancing device performance and integration density while maintaining compatibility with CMOS technology.
Implementation Method 1
The method involves electroplating semiconductor nanowires within predetermined templates with deep columnar pores
Data Source
AI summary
A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.