Isolation Pedestal for Tri-Gate Transistor Leakage Control
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Solution Overview
Problem
Conventional tri-gate transistor fabrication on bulk silicon substrates faces challenges in aligning metal gate electrodes with source and drain extension tips, leading to issues like punch-through and unwanted gate cap parasitic formation, which are not adequately addressed by existing methods combining bulk and silicon-on-insulator substrates.
Innovation Solution
The introduction of an isolation pedestal, formed by localized oxidation, between the semiconductor body and substrate, which is composed of a different semiconductor material or has a distinct width, helps in electrically isolating the channel or source/drain regions, allowing for improved gate control and reduced leakage, enabling the use of bulk substrates while mimicking silicon-on-insulator benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If tri-gate transistors are fabricated on bulk silicon substrates, then fabrication cost is reduced and manufacturing complexity is lowered, but alignment precision between metal gate electrode and source/drain extension tips deteriorates, leading to punch-through or gate cap parasitic formation
Solution Approach 1:
A sacrificial layer is introduced as an intermediary element between the source/drain extensions and the metal gate electrode. This sacrificial layer is formed at a specific depth and selectively removed to create recesses that precisely position the metal gate electrode, enabling accurate alignment without requiring direct precision control during gate formation. The sacrificial layer acts as a temporary mediator that defines the gate position and is then discarded after serving its purpose.
Solution Approach 2:
The sacrificial layer is formed in advance before the metal gate electrode deposition. By pre-forming this layer at the desired gate depth position and creating recesses through selective removal, the pathway for precise gate alignment is established beforehand. This preliminary action allows the metal gate to be deposited at the correct position without requiring high-precision alignment steps during the gate formation process itself.
2Reliability
If silicon-on-insulator substrates are used, then short-channel effects are improved, but fabrication cost increases and manufacturing complexity increases
Solution Approach 1:
Instead of using a global silicon-on-insulator substrate structure, the invention applies isolation locally by forming sacrificial layers and oxide regions only in specific areas where short-channel effect control is needed. The semiconductor body remains on a bulk substrate overall, but localized oxide regions are created beneath the channel area to provide the necessary electrical isolation and improve short-channel behavior only where required, rather than across the entire substrate.
Solution Approach 2:
The substrate is segmented into different functional regions: bulk substrate areas for mechanical support and cost-effectiveness, and localized oxide/isolated regions beneath the channel for electrical isolation and short-channel control. This segmentation allows the device to benefit from both bulk substrate advantages and SOI-like performance characteristics in the critical channel region without requiring a complete SOI substrate.
3Reliability
If metal gate electrode depth is increased to improve gate control, then gate control capability is improved, but unwanted gate cap parasitic formation increases
Solution Approach 1:
The sacrificial layer serves as a mediator that enables the metal gate electrode to be positioned at the optimal depth for gate control. By forming recesses in the sacrificial layer, the metal gate can extend deeper into the semiconductor body to improve control over the channel, while the sacrificial layer prevents the gate from directly contacting the source/drain extensions, thereby eliminating gate cap parasitic formation.
4Reliability
If source and drain extension tips are made deeper to prevent punch-through, then punch-through is prevented, but alignment precision requirements increase
Solution Approach 1:
The sacrificial layer acts as an intermediary that decouples the depth positioning of source/drain extensions from the metal gate electrode. The extensions can be formed to the required depth to prevent punch-through, and the sacrificial layer is subsequently used to define the gate position independently. This mediator allows both structures to be optimized for their respective functions without requiring precise mutual alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses sub-fin leakage, allows independent channel doping, and reduces junction leakage, enhancing transistor performance and reducing standby power consumption, while being cost-effective by starting with bulk substrates.
Implementation Method 1
An isolation pedestal is formed between the semiconductor body and the semiconductor substrate by localized oxidation
Implementation Method 2
A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body
Data Source
AI summary
Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.