Embedded Half-Bridge Circuit for Reduced Parasitic Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing half-bridge circuit packages in power applications suffer from poor space efficiency and high parasitic impacts due to electrical connections, which increase power consumption and reduce performance at high frequencies and large currents.
Innovation Solution
A packaged half-bridge circuit design featuring a carrier with a dielectric core and metallization layers, where semiconductor chips are embedded within the core and connected via a conductive connector, optimizing electrical paths and integrating driver chips and passive components for reduced parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor chips are mounted on the upper surface of the carrier, then ease of manufacture is improved, but space efficiency deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional surface mounting arrangement to a three-dimensional embedded arrangement within the dielectric core. By embedding semiconductor chips vertically within the carrier core rather than mounting them on the surface, the design achieves compact vertical stacking that reduces the horizontal footprint while maintaining manufacturing feasibility through standardized embedding processes.
Solution Approach 2:
The patent implements nesting by placing semiconductor chips inside the dielectric core of the carrier, effectively embedding one component (chips) within another (carrier core). This nested arrangement allows multiple chips to be vertically stacked within the same horizontal footprint, dramatically improving space efficiency while keeping the overall package size compact.
2Ease of manufacture
If electrical connections are made with long parasitic paths, then ease of manufacture is improved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the parasitic inductance and resistance from the electrical connection paths by directly embedding semiconductor chips within the dielectric core and establishing short vertical connections to metallization layers. This removes the long external connection paths that would otherwise introduce parasitic effects, thereby reducing power consumption in high-frequency switching applications.
Solution Approach 2:
The patent transforms the electrical connection geometry from horizontal external connections to vertical internal connections within the carrier. By routing connections vertically through the dielectric core and metallization layers, the path length is dramatically reduced, minimizing parasitic inductance and resistance while maintaining ease of manufacture through standard PCB fabrication techniques.
3Ease of manufacture
If electrical connections have high parasitic inductance, then ease of manufacture is improved, but performance at high frequencies deteriorates
Solution Approach 1:
The patent extracts parasitic inductance from the system by eliminating long external connection paths and replacing them with short vertical connections embedded within the carrier structure. This removal of parasitic elements directly improves high-frequency performance by reducing oscillations and voltage spikes during switching operations.
Solution Approach 2:
The patent changes the connection topology from external horizontal routing to internal vertical routing within the carrier core. This dimensional change creates compact current loops with minimal area, thereby minimizing parasitic inductance and improving high-frequency switching performance while maintaining compatibility with standard manufacturing processes.
4Area of stationary object
If semiconductor chips are embedded within the dielectric core, then space efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the semiconductor chips with the carrier structure by embedding them directly within the dielectric core and integrating their electrical connections with the carrier's metallization layers. This consolidation eliminates the need for separate mounting structures and external connection elements, achieving compact space utilization while actually simplifying the overall device architecture through integration.
Data Source
AI summary
A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.