Embedded HDI Core Substrate for High Pin Count Routing
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Solution Overview
Problem
Existing technologies face challenges in fabricating small devices with high-density interconnects and high pin counts, leading to congestion and increased size.
Innovation Solution
A substrate design that incorporates a high-density interconnect portion embedded in a core layer, utilizing a redistribution layer fabrication process to create interconnects with a lower minimum pitch, reducing congestion and enabling a compact form factor while maintaining high I/O pin counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-layer wiring structures are used, then routing flexibility is maintained, but signal integrity deteriorates due to crosstalk and interference
Solution Approach 1:
The patent transitions from conventional planar multi-layer wiring to a three-dimensional wiring structure where interconnect lines are embedded within the core layer in the vertical dimension. This allows signal paths to be routed through the thickness of the core layer rather than only across its surface, reducing crosstalk between adjacent lines by spatial separation in the vertical direction while maintaining routing flexibility.
Solution Approach 2:
The interconnect lines are nested within the core layer, with conductive elements embedded inside the dielectric matrix of the core layer. This nesting approach allows the wiring structure to be integrated within the existing core layer architecture rather than adding separate external wiring layers, reducing overall device complexity while improving signal integrity through better shielding and spatial separation.
2Productivity
If wiring density is increased to improve integration, then manufacturing precision requirements worsen due to difficulty in positioning and spacing
Solution Approach 1:
The interconnect lines are formed by embedding conductive materials within the core layer during the core layer fabrication process itself, before subsequent wiring layers are added. This preliminary formation of interconnects within the core layer establishes precise positioning and spacing early in the manufacturing sequence, making it easier to achieve high wiring density without compounding precision requirements through multiple subsequent alignment steps.
Solution Approach 2:
The patent merges the formation of interconnect lines with the core layer fabrication process, combining what would traditionally be separate manufacturing steps into a unified process. The conductive interconnects are deposited and patterned simultaneously with core layer structures, reducing the number of independent alignment operations required and thereby lowering overall manufacturing precision requirements while achieving high wiring density.
3Reliability
If conventional wiring methods are used, then design flexibility is maintained, but signal interference increases due to proximity of interconnect lines
Solution Approach 1:
By embedding interconnect lines within the core layer thickness rather than confining them to external wiring layers, the patent creates additional vertical spacing between signal paths. This three-dimensional arrangement reduces electromagnetic coupling and crosstalk between adjacent interconnects while still allowing flexible routing patterns to be implemented within the available vertical space, maintaining design flexibility.
Solution Approach 2:
The core layer dielectric material acts as an intermediary shielding layer between adjacent interconnect lines embedded within it. This dielectric matrix provides electrical isolation and reduces signal interference between neighboring conductors, while the flexible nature of the embedding process allows various routing configurations to be implemented without compromising shielding effectiveness.
Data Source
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AI summary
A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects.