Embedded Inductor in Semiconductor Package Using Vertical Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing inductive coils require a large area and tie bars, which limit miniaturization and complicate electrical properties in mass production, making it difficult to predict and handle their performance.
Innovation Solution
A method for manufacturing an embedded inductor within a chip package using a carrier with multiple conductive layers, where the inductor is formed by patterning and etching, allowing for miniaturization and precise control of inductor size, shape, and quality factor, eliminating the need for tie bars and enabling integration with semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional lead frame coil configuration is used, then inductor functionality is achieved, but package area becomes large limiting miniaturization
Solution Approach 1:
The patent transitions from planar coil configurations to three-dimensional vertically stacked inductor structures. Multiple conductive layers are stacked vertically with magnetic core material between them, creating a multi-layer inductor that achieves higher inductance density in the vertical dimension while reducing the horizontal footprint area.
Solution Approach 2:
The patent employs composite structures combining multiple conductive layers with magnetic core material (such as ferrite or permeable material) stacked alternately. This composite arrangement enhances the magnetic flux density and inductance while maintaining a compact form factor, resolving the contradiction between small area and functional performance.
2Stability of the object's composition
If tie bars are added to hold coil and die paddle, then structural stability is improved, but electrical properties become difficult to predict and handle
Solution Approach 1:
The patent merges the structural support function and electrical connection function into a single integrated structure. The vertically stacked conductive layers serve both as the inductor windings and as the structural framework, eliminating the need for separate tie bars that would interfere with electrical properties.
Solution Approach 2:
The patent extracts and removes the tie bar component entirely from the design. By using vertically stacked conductive layers with magnetic core material, the structure achieves inherent mechanical stability without requiring additional tie bars that would complicate electrical property prediction and manufacturing precision.
3Area of moving object
If inductor area is reduced for miniaturization, then package size decreases, but inductance value and electrical performance may be compromised
Solution Approach 1:
The patent compensates for reduced planar area by extending the inductor structure into the vertical dimension. Multiple conductive layers stacked vertically with magnetic core material create a three-dimensional inductor that achieves high inductance values through increased turn count and magnetic flux concentration in the vertical direction, maintaining power performance while minimizing footprint area.
Solution Approach 2:
The use of magnetic core material (ferrite or permeable material) between conductive layers significantly enhances the inductance density. The composite structure multiplies the effective inductance per unit area by concentrating magnetic flux through the high-permeability core material, allowing high inductance values in a compact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded inductor design reduces the package area, allows for precise control of inductor parameters, and improves electrical performance by reducing electrical losses and enabling integration with semiconductor devices for various applications, including RF and power applications without affecting soldering capabilities.
Implementation Method 1
providing a carrier having, between a first side and an opposite second side, a first conductive layer, an intermediate layer, a second conductive layer, forming an inductor and contact pads of the chip by patterning the first conductive layer from the first side of the carrier
Data Source
AI summary
A method of manufacturing an inductor embedded into a semiconductor chip package (100) is described, which method comprises providing a carrier (102; 202; 302) having, between a first side and an opposite second side, a first conductive layer (104; 503), an intermediate layer (205; 505), a second conductive layer (106; 504), forming an inductor and contact pads for the chip by patterning the first conductive layer (104; 503) from the first side of the carrier (102; 202; 302), assembling the chip and providing an encapsulation (514) and forming terminals of the package, by patterning the second conductive layer (106; 504) from the second side of the carrier.