Embedded Interconnect Die Packaging for Low-Loss Compound Substrates

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Solution Overview

Problem

Existing Chip-on-Wafer-on-Substrate (CoWoS) packages face limitations such as large size, high insertion loss, and reliability issues due to embedded interconnect dies, which also cause warpage and reduced yield in electrical routing and input/output capabilities.

Innovation Solution

Embed interconnect dies within a build-up package substrate, allowing direct bonding of device dies and packages, reducing warpage and improving yield while minimizing insertion loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If interconnect dies are embedded in CoWoS packages, then electrical interconnection is achieved, but package size increases and warpage occurs

Engineering Contradiction:

Improveelectrical interconnectionVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSVolume of moving object

Solution Approach 1:

The patent merges the interconnect die with the package substrate by forming conductive structures directly on the substrate, eliminating the need for separate embedded interconnect dies. This integration reduces package size while maintaining electrical interconnection functionality between device dies and the package substrate.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The invention extracts the interconnect die from the package structure and replaces it with conductive structures formed directly on the package substrate. This removal of the separate interconnect die component reduces package size and eliminates the warpage issues associated with embedded dies while preserving the electrical interconnection function.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If interconnect dies are embedded in CoWoS packages, then electrical connection is established, but insertion loss increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidinsertion loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent removes the embedded interconnect die from the package structure and replaces it with conductive structures formed directly on the package substrate. This extraction eliminates the additional interfaces and bonding layers that cause insertion loss, thereby reducing energy loss while maintaining electrical connection reliability.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250336901A1Packages including interconnect die embedded in package substrates

Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a build-up package substrate, which includes forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs, forming a first plurality of through-vias on the first plurality of RDLs, bonding an interconnect die to the second plurality of RDLs, encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant, and forming a third plurality of RDLs over the first encapsulant. The third plurality of RDLs are electrically connected to the first plurality of through-vias. An organic package substrate is bonded to the build-up package substrate. The build-up package substrate and the organic package substrate in combination form a compound organic package substrate. A first package component and a second package component are bonded to the compound organic package substrate, and are electrically interconnected through the interconnect die.