Embedded JFET in NMOS for Compact LED Driver ICs
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Solution Overview
Problem
Conventional high voltage start-up circuits for LED driver ICs dissipate power continuously after start-up and require extra circuit area and masks for high voltage depletion MOS, necessitating a more efficient and compact solution.
Innovation Solution
An n-channel metal-oxide field effect transistor (NMOS) with an embedded high-voltage junction gate field-effect transistor (JFET) is developed, which can be fabricated using standard high voltage processes without additional masks or processes, allowing the JFET to be integrated into the source or drain edge of the NMOS, thereby reducing the overall circuit size while maintaining similar electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high voltage depletion MOS are used to provide reference voltage or power, then the required electrical function is achieved, but extra circuit area and additional masks are required
Solution Approach 1:
The patent combines the depletion MOS functionality directly into the NMOS device by embedding a P-type well region within the N-type well region. This integration eliminates the need for separate depletion MOS devices and additional masks, achieving both reference voltage provision and area reduction simultaneously
2Reliability
If power resistor approach is used for start-up circuit, then charging current is provided during start-up, but power is continuously dissipated after start-up
Solution Approach 1:
The patent implements a dynamic start-up mechanism using the embedded depletion MOS that automatically activates during start-up to charge the capacitor and then turns off when the NMOS channel forms. This dynamic behavior eliminates continuous power dissipation while maintaining reliable start-up function
Solution Approach 2:
The start-up circuit operates periodically rather than continuously - the depletion MOS provides charging current only during the initial start-up phase when needed, and remains inactive during normal operation, reducing energy loss while ensuring reliable start-up
3Reliability
If high voltage switch type NMOS is used, then high voltage switching capability is achieved, but breakdown voltage requirements limit design flexibility
Solution Approach 1:
The patent applies local quality by creating a P-type well region specifically within the N-type well region to provide localized depletion functionality. This allows the NMOS to maintain high voltage switching capability while gaining adjustable pinch-off voltage control for enhanced design flexibility
Data Source
AI summary
A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.