Embedded Landing Pad in Through-Silicon Via for Compact Semiconductor Structures
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Solution Overview
Problem
Existing methods for manufacturing through-silicon vias (TSVs) face challenges such as large landing pads occupying space and inaccurate alignment with TSVs, which affect the efficiency and precision of electrical connections in semiconductor structures.
Innovation Solution
A semiconductor structure and manufacturing method where a conductive via penetrates a substrate with an embedded landing pad, allowing for a smaller landing pad size and increased contact area through a process involving an etch stop structure, hole formation, and conductive layer management to ensure accurate alignment and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the landing pad is made large enough to connect with TSVs, then the electrical connection reliability is improved, but the space occupancy increases
Solution Approach 1:
The landing pad is embedded within the conductive via structure, with the conductive via material surrounding the landing pad. This nesting arrangement allows the landing pad to be positioned inside the via rather than adjacent to it, reducing the overall space required while maintaining reliable electrical connection through the embedded configuration
Solution Approach 2:
The invention transitions from a planar landing pad configuration to a three-dimensional embedded structure where the landing pad is positioned vertically within the conductive via. This dimensional change allows the electrical connection to be established through the depth of the via rather than requiring extensive lateral area, thereby reducing space occupancy while maintaining connection reliability
2Reliability
If the TSVs are formed to connect with the landing pads, then the electrical connectivity is achieved, but the alignment accuracy deteriorates
Solution Approach 1:
The landing pad is formed first within the conductive via structure before the via is completely finalized. This preliminary formation of the landing pad provides a stable reference structure that guides subsequent alignment processes, ensuring that the via can be accurately positioned relative to the already-formed landing pad, thereby improving alignment accuracy while maintaining electrical connectivity
Data Source
AI summary
A semiconductor structure including a substrate, a dielectric layer, a conductive via, and a landing pad is provided. The dielectric layer is positioned on the substrate. The conductive via penetrates from a lower surface of the substrate to an upper surface of the dielectric layer. The landing pad is embedded in the conductive via.