Embedded Memory Package Layout With Bridge Die Interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor package structures are limited in the number and arrangement of memory dies that can be integrated within a single package due to routing area constraints and signal integrity considerations, which is insufficient for memory-intensive applications.
Innovation Solution
A semiconductor package structure with a memory structure embedded in the substrate below a bridge die, allowing for increased memory capacity and improved area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are integrated within a single package using conventional substrate routing, then routing area is available, but the number of memory dies that can be effectively integrated is limited due to routing area constraints and signal integrity considerations
Solution Approach 1:
The patent introduces a bridge die structure that enables three-dimensional integration of memory dies. Instead of relying solely on two-dimensional substrate routing, the bridge die creates vertical interconnect paths through the substrate, allowing memory dies to be stacked or arranged in multiple layers. This dimensional transition from planar to volumetric integration dramatically increases the number of memory dies that can be packaged within the same footprint while maintaining signal integrity through controlled interconnect paths.
2Quantity of substance
If more memory dies are integrated to increase memory capacity, then memory capacity increases, but routing area constraints and signal integrity considerations limit the effective integration
Solution Approach 1:
The bridge die acts as an intermediary structure that mediates between multiple memory dies and the substrate. It provides dedicated high-speed interconnect paths that route signals between memory dies without congesting the substrate routing layer. This intermediary bridge structure isolates signal integrity issues to localized pathways rather than affecting the entire substrate, enabling higher memory capacity integration while maintaining reliable signal transmission through controlled impedance routes.
3Ease of manufacture
If conventional substrate routing is used for connecting memory dies, then manufacturing is simpler, but the number and arrangement of chips are limited by bridge die placement constraints and routing area
Solution Approach 1:
The patent segments the interconnect function into two distinct parts: substrate-level routing for power and ground distribution, and bridge die-level routing for high-speed signal transmission between memory dies. This segmentation allows each layer to be optimized independently - the substrate maintains simple manufacturing processes while the bridge die provides flexible placement options for memory dies. The modular bridge die structure can be positioned at optimal locations to accommodate various memory die arrangements without requiring complete redesign of the substrate routing.
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, a second semiconductor die, a bridge structure and a memory structure. The substrate includes a wiring structure disposed in dielectric layers. The first semiconductor die and the second semiconductor die are disposed over the substrate. The bridge structure is embedded in the substrate. The first semiconductor die is electrically coupled to the second semiconductor die through the bridge structure. Moreover, the memory structure is embedded in the substrate and is positioned below the bridge structure.