Embedded Memory in Organic Substrate via EMIB Interconnects
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Solution Overview
Problem
Traditional high bandwidth die-to-die connections in electronic devices face challenges with complex layouts, reduced yield, high cost, and increased capacitance and resistance due to the use of silicon interposers and Through Silicon Vias (TSVs), which hinder the achievement of low latency and high bandwidth memory solutions, especially for applications like next-generation AI and graphics processors.
Innovation Solution
The implementation of an embedded Multi-die Interconnect Bridge (EMIB) or an active memory device embedded directly in the substrate, eliminating the need for silicon interposers and TSVs, allowing for direct communication between the ASIC/SOC and memory devices through a single communication channel, reducing latency and increasing bandwidth by minimizing interconnect real estate and channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon interposers with Through Silicon Vias (TSVs) are used for die-to-die connections, then bandwidth is increased, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the silicon interposer and TSV components from the traditional HBM architecture. By embedding memory devices directly into the organic substrate, the complex interposer layer and its TSV structures are removed entirely, simplifying the overall package layout while maintaining high bandwidth through direct die-to-substrate connections.
Solution Approach 2:
The patent implements nesting by embedding the memory die directly within cavities of the organic substrate. This nested configuration allows the memory devices to be integrated inside the substrate structure itself, eliminating the need for separate interposer layers and reducing overall package complexity while preserving high-speed data transfer capabilities.
2Adaptability or versatility
If Through Silicon Vias (TSVs) are used for non-die-to-die I/O/power connections, then connectivity is achieved, but capacitance and resistance increase
Solution Approach 1:
The patent removes the TSV structures entirely by eliminating the silicon interposer. Instead of using TSVs for I/O and power connections, the design employs direct bonding interfaces between the memory die and organic substrate, as well as substrate trace routing, thereby eliminating the parasitic capacitance and resistance associated with TSV implementations.
3Speed
If traditional HBM-based on-package memory solutions are used, then high bandwidth and memory capacity are achieved, but cost increases
Solution Approach 1:
The patent replaces expensive silicon interposers with cost-effective organic substrates. The organic substrate serves as the embedding medium for memory devices, eliminating the need for costly silicon interposer fabrication and assembly processes while maintaining the high bandwidth performance required for HBM applications.
Solution Approach 2:
The patent changes the fundamental material parameter from silicon-based interposers to organic substrate materials. This material substitution fundamentally alters the manufacturing process and cost structure, enabling high-bandwidth memory solutions with reduced manufacturing complexity and lower overall cost while preserving performance characteristics.
4Adaptability or versatility
If silicon interposers with TSVs are used, then die-to-die connections are established, but yield decreases
Solution Approach 1:
By removing the silicon interposer and TSV structures, the patent eliminates the complex alignment and bonding processes required for die-to-die connections through interposers. The direct embedding approach simplifies the connection establishment process, reducing process variability and improving manufacturing yield.
Data Source
AI summary
A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.