Package Substrates with Embedded Metal Pads for Reduced Bump Pitch
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Solution Overview
Problem
Conventional semiconductor device packaging technologies face challenges in achieving high yields at reduced bump pitches due to increased I/O demands, particularly in maintaining assembly integrity and reducing bump bridging and missing solder ball issues.
Innovation Solution
The fabrication process involves embedding metal features within a surface-level dielectric film, eliminating the need for solder resist and allowing direct metal-to-metal contact, enabling reduced bump pitches and higher I/O routing density through self-aligned surface finish plating and multiple layer routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semi-additive process is used with solder resist, then assembly process is simplified, but bump pitch cannot be reduced sufficiently leading to lower I/O routing density
Solution Approach 1:
The patent removes the solder resist layer from the assembly process entirely. By using exposed metal pads instead of solder resist with openings, the process eliminates the need for solder resist application, patterning, and removal steps, thereby simplifying the assembly process while enabling reduced bump pitches for higher I/O routing density
Solution Approach 2:
Instead of using solder resist to define pad locations (solder resist-defined process), the patent inverts the approach by using exposed metal pads to define connection points (metal-defined process). This inversion eliminates the intermediary solder resist layer and enables direct metal-to-metal contact, achieving both simplified processing and reduced bump pitch capability
2Quantity of substance
If bump pitch is reduced to increase I/O routing density, then more I/O connections are achieved, but manufacturing precision requirements increase significantly
Solution Approach 1:
The patent performs preliminary self-alignment by forming the metal pad pattern first, then using it as the reference for subsequent solder ball placement. The metal pad edges serve as built-in alignment features that guide the bump placement process, eliminating the need for complex alignment procedures and enabling reduced bump pitches with maintained precision
Solution Approach 2:
The metal pad structure serves multiple functions simultaneously: it provides the connection terminal, defines the alignment reference, and acts as the target for solder ball placement. This self-service approach eliminates the need for separate alignment marks and reference features, simplifying the manufacturing process while enabling higher precision at reduced pitches
3Reliability
If solder resist is used to define pads, then pad definition is achieved, but BHAST reliability issues occur and assembly yields decrease
Solution Approach 1:
The patent converts the potential harm of exposed metal (oxidation, contamination) into a benefit by using the metal pad as a self-aligning reference feature and direct connection point. The exposed metal provides superior electrical contact and alignment precision that outweighs the risks, especially when combined with appropriate surface finish processes
Solution Approach 2:
The patent eliminates the solder resist intermediary layer that causes BHAST (Ball Grid Array Solderability and Strength) reliability issues. By enabling direct metal-to-solder ball contact, the process removes the interface between solder resist and solder that is prone to delamination and reliability failures, achieving superior assembly reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances I/O routing density and assembly reliability by mitigating BHAST reliability issues and allowing for smaller bump pitches without increasing assembly complexity, thereby improving chip-substrate assembly yields.
Implementation Method 1
the conducting traces and vias 125 are electroplated on the metallic seed layer 115
Implementation Method 2
A via hole 109 is then laser drilled in the dielectric build up layer 104
Implementation Method 3
a solder ball 150 into the solder resist mask opening which is then reflowed
Data Source
AI summary
Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.