Embedded Microelectronic Chip Structure for Compact Assembly
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Solution Overview
Problem
Conventional semiconductor chip arrangements face challenges in minimizing volume and interconnection complexity, particularly in compact portable devices and data servers, where reducing chip thickness and interconnection impedance is essential without increasing assembly size or power consumption.
Innovation Solution
A microelectronic structure with a first semiconductor chip having a cavity extending from its rear surface, accommodating an additional microelectronic element within the cavity, and utilizing vias with varying diameters to provide connectivity and compact assembly capabilities, allowing for the integration of multiple functionalities within a single chip volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor chip arrangements are used, then manufacturing simplicity is maintained, but volume and interconnection complexity increase
Solution Approach 1:
The patent embeds additional microelectronic elements directly within cavities of the semiconductor chip body, creating a nested configuration where one chip structure contains another. This nesting approach minimizes overall assembly volume while reducing the number of external interconnections needed, as embedded elements connect through internal vias rather than external traces.
Solution Approach 2:
The patent transitions from conventional planar chip arrangements to a three-dimensional structure by forming cavities within the chip body and embedding elements vertically. This dimensional change allows multiple functional elements to coexist within the same horizontal footprint, reducing volume while simplifying interconnection paths through vertical vias.
2Volume of moving object
If chip thickness is reduced to minimize volume, then volume decreases, but physical stability deteriorates
Solution Approach 1:
By embedding additional microelectronic elements within cavities of the chip body, the patent creates a nested structure that utilizes internal space rather than increasing external dimensions. This allows volume reduction through efficient space utilization while maintaining structural integrity through the embedded configuration.
Solution Approach 2:
The patent creates a composite chip structure combining the original semiconductor chip material with embedded microelectronic elements and encapsulant material. This composite approach allows thinning of the overall assembly while maintaining stability through the distributed structure of embedded elements throughout the chip body.
3Area of stationary object
If multiple chips are stacked to reduce horizontal area, then area decreases, but vertical height and interconnection complexity increase
Solution Approach 1:
The patent merges multiple functional elements into a single integrated chip structure by embedding additional microelectronic elements within the same chip body. This consolidation eliminates the need for separate stacked chips, reducing both horizontal area and vertical height while simplifying interconnections through internal pathways rather than external interfaces.
Solution Approach 2:
By nesting embedded elements within cavities of the chip body, the patent achieves multi-functionality within a single chip volume rather than requiring multiple stacked chips. This nested configuration minimizes both the horizontal footprint and vertical height of the overall assembly.
Data Source
AI summary
A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.