Embedded Microelectronic Die Mounting Substrate for High Bandwidth
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Solution Overview
Problem
Current semiconductor microelectronic device packaging technologies face challenges in optimizing the placement and integration of microelectronic dies within processor footprints to minimize physical signal paths, reduce inductive effects, and achieve uniform heat soak, while maintaining high I/O density and bandwidth.
Innovation Solution
The embedding of microelectronic dies within the mounting substrate, either partially or entirely, allows for asymmetric or symmetric placement relative to the processor, utilizing die-side and land-side build-ups, and through-substrate vias to reduce physical signal lengths and enhance heat distribution, thereby improving electrical performance and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microelectronic dies are embedded within the mounting substrate, then physical signal paths are reduced and inductive effects are minimized, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The microelectronic die is embedded within a cavity formed in the mounting substrate, creating a nested structure where the die sits inside a recessed area. This nesting approach reduces the overall profile and signal path length while maintaining electrical performance.
Solution Approach 2:
The embedding technique transitions from planar surface mounting to three-dimensional integration by creating cavities and using vertical build-up layers. This dimensional change allows signals to travel shorter distances through the substrate thickness rather than across the surface.
2Temperature
If asymmetric or symmetric placement of microelectronic dies is used, then heat distribution is improved, but placement precision and alignment difficulty increase
Solution Approach 1:
The mounting substrate employs asymmetric placement of microelectronic dies relative to the processor, positioning them at different locations to create more uniform heat distribution patterns. This asymmetric arrangement prevents heat concentration in specific areas while maintaining electrical connectivity.
Solution Approach 2:
Different regions of the mounting substrate are designed with varying thermal properties and die placement configurations. The build-up layers and cavity structures are locally optimized to manage heat flow from specific die locations, creating zone-specific thermal management.
3Productivity
If die-side and land-side build-ups are utilized, then I/O density and bandwidth are increased, but manufacturing processes and device complexity increase
Solution Approach 1:
The mounting substrate is divided into distinct functional regions including die-side build-up areas, land-side build-up areas, and cavity regions. Each segment serves a specific purpose in achieving high I/O density while managing the manufacturing complexity through modular construction.
Solution Approach 2:
The build-up layers serve multiple functions simultaneously: they provide electrical connectivity, mechanical support, thermal management pathways, and define cavity boundaries. This multi-functionality increases I/O capability while consolidating manufacturing steps.
Data Source
AI summary
A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.