Embedded MIM Capacitor in Monolithic 3D IC Structure
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Solution Overview
Problem
Monolithic 3D integrated circuit structures face challenges in controlling manufacturing yield and minimizing undesirable boundary effects due to minimal spacing between circuit components, which complicates the design and functionality of embedded capacitors.
Innovation Solution
The integration of a metal-insulator-metal (MIM) capacitor within the dielectric layer of a 3D IC structure, with contacts extending through the semiconductor and dielectric layers to access the capacitor layers, allowing for reduced silicon area usage and closer placement to other circuitry, is implemented.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If minimal spacing between circuit components is used in monolithic 3D structures, then silicon area is reduced, but manufacturing yield control and boundary effects become problematic
Solution Approach 1:
The patent embeds the MIM capacitor within the dielectric layer between transistor layers, utilizing the vertical dimension of the 3D structure rather than placing capacitors in the planar layout. This dimensional transition allows capacitors to be integrated without increasing the silicon footprint, while the dielectric embedding provides manufacturing control and reduces boundary effects by surrounding the capacitor electrodes completely.
2Area of moving object
If MIM capacitor is embedded within dielectric layer, then silicon area usage is reduced and closer placement to circuitry is enabled, but capacitor fabrication complexity increases
Solution Approach 1:
The patent merges the capacitor fabrication process with the existing dielectric layer formation process in the 3D IC structure. The MIM capacitor electrodes are formed as conductive layers within the dielectric material using the same deposition and patterning tools already required for the transistor interconnects, eliminating the need for separate capacitor fabrication equipment or processes.
Data Source
AI summary
Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.