Embedded MRAM Layout With Aligned Source Line and Symmetric Plugs
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Solution Overview
Problem
Conventional MRAM fabricating processes lack integrity, necessitating a new method for forming MRAM structures with improved alignment and symmetry in the source and drain metal layers.
Innovation Solution
The method involves forming an embedded MRAM structure with a substrate divided into memory and logic device regions, where source and drain plugs are symmetrically arranged relative to a word line, and metal layers are aligned to ensure the source line is at the same height as the second metal layer, facilitating a symmetric layout that enhances structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional MRAM fabricating processes are used, then the manufacturing process can be completed, but the structural integrity and alignment of source and drain metal layers are insufficient
Solution Approach 1:
The source line and second metal layer are formed at the same height during the same fabrication stage, establishing proper alignment before subsequent processing steps. This preliminary action ensures that the alignment requirement is met early in the process, preventing compounding errors in later stages.
Solution Approach 2:
The fabrication process merges the formation of the source line and second metal layer into a single simultaneous operation, where both structures are created at the same height level during the same deposition and patterning sequence. This combining approach ensures intrinsic alignment rather than requiring separate alignment steps.
2Stability of the object's composition
If source and drain plugs are arranged asymmetrically as in conventional methods, then the fabrication process is simpler, but the structural integrity and symmetry of the MRAM structure are compromised
Solution Approach 1:
The invention deliberately employs asymmetric photomask patterns and etching conditions to achieve symmetric physical structures. By using asymmetric processing parameters (such as different etch selectivities or mask orientations) on asymmetrically positioned plugs, the method compensates for layout asymmetry and produces symmetric final structures with matching dimensions and properties.
Solution Approach 2:
The fabrication process changes key parameters such as etch depth, deposition thickness, and patterning conditions to ensure that source and drain plugs achieve identical dimensions and orientations despite their asymmetric positions relative to the transistor. This parameter adjustment ensures structural symmetry and integrity.
Data Source
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AI summary
An embedded MRAM structure is disclosed which comprises a substrate (10) carrying an interconnection (70) including at least four metal layers (M1-M4) and three via plug levels (V1-V3), divided into a logic device region (60) and a memory cell region (50), wherein a memory cell comprises a transistor active area, a gate word line (WL1), a source plug (20) and a drain plug (22) in mirror symmetric arrangement, a source line (SL) formed in M2, and an MTJ formed in M3 on a tungsten plug (W) in the drain interconnection stack.