Embedded MTJ Memory Structures Eliminating Conductive Vias in BEOL
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Solution Overview
Problem
The integration of memory devices within metallization layers in integrated circuits, particularly for MRAM technology, is challenging due to the height mismatch between magnetic tunnel junction (MTJ) stacks and metallization vertical interconnect access (via) in BEOL processing, making simple substitution impractical and requiring complex arrangements.
Innovation Solution
A method of fabricating integrated circuits with memory structures by forming lower and upper conductive interconnects in dielectric layers, depositing MTJ layers, and etching to create a memory structure directly over a dielectric pillar, eliminating the need for conductive vias between metallization layers, allowing direct contact between MTJ structures and adjacent metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MTJ stacks are placed within metallization layers using conventional BEOL processing, then memory density increases, but the height mismatch between MTJ stacks and metallization vias makes integration difficult and requires complicated arrangements
Solution Approach 1:
The patent segments the interconnect structure by eliminating the conductive via component entirely. Instead of having a continuous conductive path through vias, the design separates the lower and upper metallization layers, with the MTJ stack forming a direct vertical interconnect between them. This segmentation resolves the height mismatch issue by removing the via structure that caused the complexity.
Solution Approach 2:
The patent inverts the conventional approach by making the MTJ stack serve dual functions: as the memory element and as the vertical interconnect. Instead of using separate vias for interconnection and placing MTJ stacks beside them, the MTJ stack itself becomes the conductive pathway, eliminating the need for additional via structures and simplifying the overall integration.
2Ease of manufacture
If simple substitution of MTJ stacks at metallization via locations is attempted, then fabrication process remains simple, but the height mismatch between MTJ stacks and metallization vias makes it impractical
Solution Approach 1:
The patent merges the MTJ stack structure with the vertical interconnect function. By forming the MTJ stack to extend from the lower metallization layer to the upper metallization layer, the design combines the memory element and the interconnect into a single integrated structure. This merging eliminates the height alignment issue between separate MTJ stacks and vias, as they are now part of the same continuous structure.
3Reliability
If conductive vias are used to connect lower and upper metallization layers with MTJ stacks, then electrical connection is achieved, but the additional via structures increase device complexity and fabrication time
Solution Approach 1:
The patent extracts and removes the conductive via structure from the conventional BEOL processing sequence. By eliminating the via formation steps (via etching, via filling, and via planarization), the design reduces fabrication time and complexity while maintaining reliable electrical connection through the integrated MTJ stack structure that directly connects the metallization layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of high-density memory structures with improved performance, reduced cost, and time efficiency, allowing for seamless integration of logic and memory structures while increasing scaling capabilities by eliminating the need for conductive vias, thus addressing the height mismatch issue.
Implementation Method 1
depositing magnetic tunnel junction (MTJ) layers over the bottom electrode layer
Implementation Method 2
depositing a top electrode layer over the MTJ layers
Data Source
AI summary
Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming from a first metallization layer a first lower conductive interconnect in a first region of a dielectric layer and a second lower conductive interconnect in a second region of the dielectric layer. The method includes forming a memory structure in the first region. Further, the method includes depositing an interlayer dielectric over the first region and over the second region. Also, the method includes forming from a second metallization layer a first upper conductive interconnect over the interlayer dielectric, wherein the first upper conductive interconnect is coupled to the memory structure.