Embedded Multilayer Capacitor via Vertical Vias
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Solution Overview
Problem
Conventional multilayer chip capacitors embedded in printed circuit boards are prone to chipping and cracking, leading to reliability issues and increased manufacturing costs due to the need for precise laser processing and alignment of via holes, which can result in mechanical damage during handling and warping of the board.
Innovation Solution
The design features a multilayer chip capacitor with internal electrodes connected via vias that extend vertically within the capacitor body, with top and bottom terminals connected to conductive layers on the printed circuit board, eliminating the need for external electrodes and reducing the risk of mechanical damage by allowing the capacitors to be arranged horizontally and connected in parallel, thus preventing chipping and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a thin multilayer chip capacitor is used to embed the capacitor in the board, then the space utilization is improved, but the mechanical strength deteriorates causing chipping and cracking
Solution Approach 1:
The capacitor is divided into multiple thin dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with internal electrodes interleaved between them. This segmentation allows the capacitor to achieve the required capacitance in a thinner overall structure while maintaining mechanical integrity through the distributed layer structure.
Solution Approach 2:
The capacitor employs composite material structure combining multiple dielectric materials with different properties. The first dielectric layer has different characteristics than the second and third dielectric layers, creating a composite structure that optimizes both electrical performance and mechanical strength to prevent chipping and cracking.
2Manufacturing precision
If conventional laser processing is used to couple substrate wiring to external electrodes, then the manufacturing precision is improved, but the manufacturing cost increases significantly
Solution Approach 1:
The invention extracts and eliminates the need for precise laser drilling of via holes by removing external electrodes. Instead, the internal electrodes extend directly to the side surfaces of the capacitor body, allowing direct coupling with substrate wiring through simple conductive paste application, thereby eliminating the expensive and precision-critical laser processing step.
Solution Approach 2:
The invention replaces the expensive laser processing method with a cheaper alternative using conductive paste for electrical coupling. This substitution uses a lower-cost, more flexible manufacturing approach that does not require high-precision equipment while achieving the same functional result.
3Adaptability or versatility
If the board is warped during manufacturing or handling, then the manufacturing flexibility is improved, but the capacitor reliability deteriorates due to mechanical damage
Solution Approach 1:
The invention inverts the traditional electrode configuration by placing electrodes on the side surfaces rather than on the top and bottom external surfaces. This inversion allows the capacitor to be embedded horizontally in the substrate, making the capacitor structure adaptable to board warping while maintaining reliable electrical connections that are not susceptible to mechanical damage from bending stresses.
Solution Approach 2:
The capacitor employs a flattened, thin-profile structure with electrodes extending to the side surfaces, creating a flexible configuration that can accommodate board warping during manufacturing and handling. This structure acts like a flexible element that can withstand deformation without causing mechanical damage to the capacitor or compromising its reliability.
Data Source
AI summary
The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor has a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.


