Embedded Network-on-Chip Routing for 2.5D and 3D IC Connectivity
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Solution Overview
Problem
Existing configurable integrated circuits face challenges in efficiently routing data between multiple integrated circuits due to congestion and limitations in connectivity, particularly in 2.5D and 3D assemblies, which affect performance in big-data and fast-data applications.
Innovation Solution
The integration of embedded networks-on-chip (NOCs) across the central region of each integrated circuit, coupled with external conductors, creates 2.5D and 3D connectivity layers that extend across multiple ICs, facilitating efficient data transmission through interface regions and buffer circuits, thereby enhancing data routing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional routing methods are used in configurable integrated circuits, then device complexity is reduced, but data transmission efficiency deteriorates due to congestion and connectivity limitations
Solution Approach 1:
The patent introduces a hierarchical routing architecture that adds a vertical dimension to traditional planar routing. Multiple routing layers are stacked in three-dimensional space, allowing data to transmit across layers via through-silicon vias (TSVs) or microbumps. This dimensional expansion provides additional pathways for data flow, effectively reducing congestion on any single layer while maintaining manageable complexity through structured layer organization.
Solution Approach 2:
The routing resource is divided into multiple independent routing layers, each handling specific data flows or functional domains. This segmentation allows parallel data transmission across different layers without interference, improving overall throughput. Each layer can be independently configured and optimized, reducing the complexity of managing all routing resources as a single monolithic structure.
2Adaptability or versatility
If more routing paths are added to increase connectivity, then data transmission efficiency improves, but device complexity increases due to additional routing infrastructure
Solution Approach 1:
The patent designs universal routing resources that can be dynamically allocated and configured for different data flows and applications. The same physical routing infrastructure serves multiple functions through programmable routing logic and configurable connection matrices. This multi-functionality allows high adaptability and connectivity without proportionally increasing physical infrastructure complexity, as the system can reconfigure existing resources to meet different connectivity requirements.
Solution Approach 2:
The routing architecture employs dynamic, reconfigurable connections rather than fixed static routing. Routing paths can be programmatically adjusted based on real-time traffic patterns and performance requirements. This dynamic configurability enables the system to adapt to varying connectivity demands without requiring dedicated physical paths for every possible connection, thereby achieving high versatility with controlled infrastructure complexity.
3Productivity
If three-dimensional routing layers are implemented, then data transmission efficiency improves through reduced congestion, but manufacturing precision requirements worsen due to alignment tolerances
Solution Approach 1:
The patent incorporates compensation mechanisms and alignment tolerance designs in the routing layer structure. Features such as alignment marks, self-aligning structures, and redundant connection paths are built into the manufacturing process to accommodate variations. These preemptive measures cushion against misalignment errors, allowing three-dimensional routing layers to be manufactured within practical precision tolerances while still achieving the desired data transmission efficiency and reduced congestion.
Data Source
AI summary
An integrated circuit includes a central region having logic circuits and networks-on-chip. Each of the networks-on-chip traverses the central region. The integrated circuit also includes an interface region having input and output buffer circuits. The networks-on-chip are configurable to exchange data between the logic circuits and the input and output buffer circuits. One of the networks-on-chip is configurable to place each source that receives the data from one of the logic circuits at one of multiple locations in the one of the networks-on-chip. The one of the networks-on-chip is also configurable to place each sink that provides the data to one of the logic circuits at one of the multiple locations in the one of the networks-on-chip. The input and output buffer circuits are coupled to exchange the data with an external device.