Embedded Semiconductor Package Layout for Shorter Conduction Paths
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Solution Overview
Problem
As the number of functional chips in a semiconductor package increases, conduction paths between the substrate and various functional chips also increase, leading to transmission loss and adverse effects on electrical performance.
Innovation Solution
A semiconductor package structure is designed with a substrate, a first electronic component embedded in the substrate, and a reinforcement supporting a second electronic component, featuring a conductive structure for heat dissipation and reduced conduction paths through a cavity and conductive pillars for vertical electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of functional chips is increased, then the functionality and performance of the semiconductor package is improved, but the number of conduction paths increases leading to increased transmission loss
Solution Approach 1:
The patent transitions from planar conduction paths to three-dimensional vertical conduction paths by embedding electronic components within the substrate using cavities and conductive pillars. This dimensional change reduces the horizontal distance signals must travel, thereby reducing transmission loss while accommodating multiple functional chips in a compact vertical arrangement.
Solution Approach 2:
The patent embeds electronic components inside cavities formed within the substrate, creating a nested structure where components are housed within the substrate volume rather than being mounted on its surface. This nesting approach allows multiple components to coexist in a compact space while maintaining short conduction paths through the substrate's internal structure.
2Adaptability or versatility
If more functional chips are added to the package, then the device capabilities are enhanced, but the package size must be increased
Solution Approach 1:
The patent utilizes the vertical dimension by embedding components at different depths within the substrate using cavities and conductive pillars. This allows multiple functional chips to be stacked vertically rather than arranged horizontally, significantly reducing the package's footprint while maintaining enhanced device capabilities.
Solution Approach 2:
Electronic components are nested within cavities formed in the substrate, allowing multiple components to occupy the same horizontal footprint at different vertical levels. This nesting strategy enables high-density integration of functional chips without increasing the overall package size.
3Ease of manufacture
If traditional packaging methods are used with multiple chips on the substrate surface, then the manufacturing process is simple, but transmission loss increases and electrical performance deteriorates
Solution Approach 1:
The patent employs vertical embedding of components through cavities and conductive pillars, transforming the traditional surface-mount approach into a three-dimensional integration scheme. This dimensional transition reduces conduction path lengths and improves electrical performance while maintaining manufacturing feasibility through established semiconductor fabrication techniques.
Solution Approach 2:
The substrate acts as an intermediary structure containing embedded cavities and conductive pillars that facilitate short-distance electrical connections between components. This intermediary architecture enables improved electrical performance by providing direct vertical conduction paths while the substrate's existing manufacturing processes maintain ease of production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces transmission loss, improves electrical performance, and allows for a smaller package size while increasing manufacturing yield and reducing costs by embedding known-good device packages and simplifying the manufacturing process.
Implementation Method 1
The first conductive structure extends along a lateral surface of the first electronic component and configured for providing heat dissipation for a second electronic component outside of the interposer
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first electronic component, and an electronic device. The first electronic component is disposed over the substrate. The electronic device is at least partially embedded in the substrate. The electronic device includes a second electronic component and a reinforcement. The second electronic component is configured for providing a regulated voltage to the first electronic component. The reinforcement supports the second electronic component.