Embedded PMOS SCR ESD Protection with Suppression Rings
Solution Overview
Problem
Advanced ICs with smaller transistors are susceptible to electro-static-discharge (ESD) damage due to thinner gate oxides and lower power supply voltages, leading to latch-up and thermal failures, as existing ESD protection structures struggle to maintain a safe design window with reduced breakdown voltages and increased trigger voltages.
Innovation Solution
Integrating a p-channel transistor (PMOS) within the Silicon-Controlled Rectifier (SCR) structure to temporarily suppress guard rings during ESD events, allowing the SCR to turn on at a lower trigger voltage while maintaining a high holding voltage, thus optimizing the ESD protection within the safe design window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard SCR structure is used with guard rings for latch-up suppression, then reliability against latch-up is improved, but trigger voltage increases above the safe design window
Solution Approach 1:
A PMOS trigger transistor is introduced as an intermediary device between the ESD pulse source and the SCR structure. The PMOS transistor acts as a mediator that can be selectively activated to trigger the SCR, allowing control over the trigger voltage level while maintaining the guard rings for latch-up suppression. This intermediary enables the SCR to trigger at a lower voltage than the breakdown voltage while still benefiting from the guard rings' protective effect.
2Use of energy by moving object
If device size is reduced to shrink transistor dimensions, then power consumption is reduced, but susceptibility to ESD damage increases
Solution Approach 1:
The PMOS trigger transistor is nested within the SCR structure, with the transistor integrated into the SCR's cell layout. This nested configuration allows the trigger device to be embedded within the protection structure itself, enabling compact design that maintains both the low-power benefits of small transistors and the ESD protection functionality through the integrated trigger mechanism.
3Reliability
If breakdown voltage is reduced to operate within safe design window, then ESD protection safety is improved, but trigger voltage may become insufficient to activate protection
Solution Approach 1:
The PMOS trigger transistor is configured to activate the SCR in advance before the breakdown voltage is reached. By using the PMOS transistor to initiate the SCR conduction at a lower voltage level, the protection mechanism is activated preliminarily, preventing the voltage from rising to dangerous levels while ensuring the protection is triggered at an appropriate voltage threshold.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the trigger voltage below the breakdown voltage, enhancing ESD protection by ensuring the ESD structure operates within the safe design window, reducing susceptibility to latch-up and thermal failures, and improving reliability.
Implementation Method 1
The triggering PMOS transistor floods the guard rings with carriers to temporarily suppress their effect
Implementation Method 2
The SCR is a PNPN structure from anode A to cathode K that shunts current from node A to node K
Implementation Method 3
ESD failures that occur in the factory contribute to lower yields. ESD failures may also occur in the field when an end-user touches a device.
Data Source
AI summary
An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.