Embedded Power Semiconductor Assembly With Insulated Heat Path
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Solution Overview
Problem
Existing power semiconductor assemblies face challenges in achieving low thermal resistance, low stray inductance, and low production costs while effectively insulating embedded chips from heatsinks, particularly in ceramic substrate embedding and laminate integration.
Innovation Solution
A power semiconductor assembly design that includes a power semiconductor die embedded within a printed circuit board (PCB) with a metal substrate recess, coupled to a power electronic substrate via a solder joint and insulated by a dielectric material layer, which is further coupled via a fused joint, ensuring electrical isolation and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If an embedded chip is used in power semiconductor assembly, then thermal resistance and stray inductance are reduced, but electrical insulation between the embedded chip and heatsink becomes challenging
Solution Approach 1:
A ceramic substrate is introduced as an intermediary component between the embedded power semiconductor chip and the heatsink. The ceramic substrate provides both thermal conduction pathways and electrical insulation, mediating the conflicting requirements of heat dissipation and electrical isolation. The ceramic material's inherent properties allow it to conduct heat while maintaining electrical breakdown strength.
Solution Approach 2:
The assembly utilizes composite material structures including the ceramic substrate combined with laminate materials, and the integration of metal substrates with ceramic layers. These composite structures provide tailored thermal and electrical properties, combining the high thermal conductivity of ceramics with the insulating properties of laminates to simultaneously achieve low thermal resistance and high electrical insulation.
2Temperature
If ceramic substrate embedding is implemented, then thermal management is improved, but fabrication complexity increases due to unresolved issues in fabricating and embedding ceramic substrates
Solution Approach 1:
The ceramic substrate is prepared in advance with pre-defined embedding cavities and electrical insulation structures before the power semiconductor chip is mounted. This preliminary preparation of the ceramic substrate simplifies the subsequent embedding process and reduces fabrication complexity by separating the ceramic fabrication steps from the chip assembly steps.
Solution Approach 2:
The power semiconductor chip is embedded within a cavity in the ceramic substrate, which itself is integrated into the laminate structure. This nested arrangement allows the ceramic substrate to be embedded within the larger laminate assembly, creating a hierarchical structure that simplifies manufacturing by allowing each component to be prepared and assembled in a systematic sequence.
3Ease of manufacture
If traditional power semiconductor assembly methods are used, then production costs are higher, but material consumption and chemical waste increase
Solution Approach 1:
Multiple functions are merged into integrated structures: the ceramic substrate simultaneously provides electrical insulation, thermal conduction, and mechanical support; the laminate structure integrates multiple layers for electrical connection and structural integrity. This functional integration reduces the number of separate components and materials needed, thereby reducing material consumption and associated chemical waste.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces material consumption, ohmic losses, and chemical waste, enabling energy and resource savings, and provides reliable electrical insulation and heat management for high-power applications.
Implementation Method 1
a dielectric material layer arranged between the second side of the printed circuit board and the power electronic substrate
Implementation Method 2
coupled via a first solder joint to a metal layer on the second side of the printed circuit board
Implementation Method 3
coupling via a fused joint formed using the dielectric material layer the power electronic substrate to the printed circuit board
Data Source
AI summary
A power semiconductor assembly includes: a power semiconductor die having opposing first and second sides; a metal substrate having opposing first and second sides, the first side having a recess in which the power semiconductor die is arranged such that the second side of the power semiconductor die faces a bottom side of the recess; a printed circuit board (PCB) having opposing first and second sides, the power semiconductor die and metal substrate being embedded within the PCB; a power electronic substrate arranged below the second side of the PCB and coupled via a solder joint to a metal layer on the second side of the PCB; and a dielectric material layer arranged between the second side of the PCB and the power electronic substrate and arranged laterally next to the solder joint, the dielectric material layer coupling the PCB to the power electronic substrate via a fused joint.