Embedded RRAM Structure for Source/Drain Contact Protection
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Solution Overview
Problem
The integration of resistive random-access memory (RRAM) structures with transistor structures in integrated circuits poses challenges due to potential damage to the underlying source/drain structures and thickness variations in the RRAM material, leading to low device reliability and performance issues.
Innovation Solution
A method for fabricating a semiconductor device with an embedded RRAM structure where the RRAM is sandwiched between the source/drain contacts and a metal electrode, allowing for controlled thickness of the resistive material through blanket deposition, thereby avoiding direct contact with the source/drain structures and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If RRAM structures are formed directly in contact with source/drain structures, then the manufacturing process is simpler, but the source/drain structures may be damaged and device reliability decreases
Solution Approach 1:
The patent introduces an intermediary layer (first conductor layer) between the source/drain structures and the RRAM resistive material. This conductor layer acts as a buffer that prevents direct contact damage while still enabling electrical connection, thus resolving the contradiction between manufacturing simplicity and device reliability.
2Device complexity
If RRAM material thickness is not precisely controlled, then the manufacturing process is less complex, but thickness variations lead to performance issues
Solution Approach 1:
The patent replaces mechanical/contact-based thickness control with a field-based approach using blanket deposition. This deposition method provides uniform thickness control across the entire substrate through controlled material deposition, achieving precise thickness control without complex mechanical positioning or contact-based processes.
3Area of moving object
If line and via pitch in interconnect layers is scaled down, then the circuit density increases, but the space between RRAM structures is reduced and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar (2D) RRAM structure formation to a three-dimensional approach by using blanket deposition that covers the entire substrate uniformly. This allows RRAM structures to be formed in the vertical dimension above the scaled-down interconnect layers, maintaining adequate spacing while achieving high circuit density through vertical integration rather than lateral scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and yield of the embedded RRAM structure, leading to enhanced overall performance and reliability of integrated circuits by preventing structural damage to the source/drain structures and ensuring precise control over the RRAM thickness.
Implementation Method 1
a layer of resistive material formed over the pair of S/D contacts. Since the layer of resistive material is formed by a blanket deposition process, the thickness of the RRAM structure can be well-controlled
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.