Embedded Semiconductor Device Manufacturing Process
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in precisely controlling wire-bonding heights to prevent short circuits and excess thickness in chip package structures, particularly due to the need for precise placement of pads on a substrate surface.
Innovation Solution
A manufacturing process involving a substrate with multiple metal layers and conductive structures, where a semiconductor device is embedded within insulation layers, allowing for precise electrical connections and eliminating the need for subsequent molding steps, thereby simplifying the process and preventing wire bridging issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding height is increased to prevent short circuits, then reliability is improved, but package thickness increases
Solution Approach 1:
The invention transitions from planar wire-bonding to three-dimensional vertical interconnections through through-holes. Conductive structures are formed vertically through the substrate thickness, enabling electrical connections without requiring exaggerated wire-bonding heights, thus preventing short circuits while maintaining compact package thickness.
Solution Approach 2:
The invention introduces an intermediary embedding structure where semiconductor devices are embedded within the substrate. This embedding approach provides a stable intermediate platform that eliminates the need for precise wire-bonding height control, as connections are established through vertical conductive paths rather than horizontal wire bonds.
2Ease of manufacture
If pads are disposed on the same surface to simplify layout, then manufacturing complexity is reduced, but wire-bonding precision requirements increase
Solution Approach 1:
The invention inverts the conventional approach by forming conductive structures vertically through the substrate rather than horizontally across the surface. This inversion transforms the manufacturing challenge from controlling wire-bonding height precision to forming vertical through-holes and filling them with conductive material, which simplifies the overall manufacturing process.
Solution Approach 2:
The invention replaces the mechanical wire-bonding process with a chemical/electrical approach. Instead of mechanically placing and bonding wires with precise height control, the conductive structures are formed through chemical etching of through-holes and electroplating or other deposition methods, eliminating the need for precise mechanical wire-bonding control.
3Volume of moving object
If conventional chip package structure with cavity is used, then chip accommodation is achieved, but molding process complexity increases
Solution Approach 1:
The invention merges the chip mounting process with the substrate fabrication process. Semiconductor devices are embedded directly into the substrate during the same manufacturing sequence, combining what would traditionally be separate steps (chip mounting and encapsulation molding) into a single integrated process, thereby reducing overall process complexity.
Solution Approach 2:
The invention performs preliminary embedding of semiconductor devices into the substrate before final encapsulation. By pre-positioning and securing chips within the substrate structure through the embedding process, the subsequent encapsulation step becomes simpler, as devices are already fixed in place rather than requiring complex molding to secure them.
Data Source
AI summary
A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.