Embedded Semiconductor Stack Structure for Compact Carrier Boards
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving compactness and simplifying the manufacturing process due to wire-bonding methods and the need for multiple solder wire pads, which increase package height and complexity, limiting the number of stacked semiconductor chips and area efficiency.
Innovation Solution
A stack structure of carrier boards with embedded semiconductor components, where through holes in each board house the components, sealed with protecting layers, and a dielectric layer fixes them, with circuit build-up structures and electroplated holes for electrical connections, allowing for modularized and space-efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding method is used to electrically connect stacked semiconductor chips, then electrical connection is achieved, but package height increases due to arc wires
Solution Approach 1:
The patent transitions from planar wire-bonding connection to three-dimensional vertical connection through through-holes. Conductive structures are formed extending vertically through the substrate to connect stacked semiconductor chips, eliminating the need for arc-shaped wire bonds and reducing package height while maintaining electrical connectivity.
2Adaptability or versatility
If multiple solder wire pads are installed on circuit board to support more stacked layers, then electrical functionality is improved, but circuit board area increases
Solution Approach 1:
The patent moves electrical connections from the horizontal plane (surface-mounted solder wire pads) to the vertical dimension (through-holes penetrating the substrate). This allows multiple semiconductor chips to be stacked and connected vertically through the substrate thickness, increasing electrical functionality without expanding the circuit board footprint.
Solution Approach 2:
The substrate is designed with through-holes (porous structure) that allow conductive structures to pass completely through the substrate thickness. This enables vertical electrical connections between stacked chips, providing multiple connection paths within the substrate volume rather than requiring additional surface area.
3Area of stationary object
If thin circuit layout is installed on circuit board to reduce area, then area is reduced, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent relocates circuit routing from the two-dimensional surface to the three-dimensional volume of the substrate through through-holes. This vertical routing approach reduces the required surface area while providing adequate space for conductive structure formation and alignment, thereby maintaining manufacturing precision.
4Productivity
If semiconductor chips are stacked on circuit board to increase density, then package capacity increases, but process complexity increases due to multiple solder wire pads and wire-bonding
Solution Approach 1:
The patent combines multiple functions into the through-hole structure: mechanical support for stacked chips, electrical connection pathways, and structural alignment features. This integration eliminates the need for separate wire-bonding processes and multiple solder wire pads, simplifying the manufacturing process while maintaining high package density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the density and functionality of semiconductor packages, simplifies the manufacturing process, and reduces costs by embedding components within the boards, enabling more efficient use of space and flexible configuration.
Implementation Method 1
a dielectric layer is formed between another surfaces of the first and second carrier boards, both of the another surfaces being surfaces without any protecting layer, to fill part of the dielectric layer in the through holes of the first and second carrier boards to fix the first and second semiconductor components
Implementation Method 2
a plurality of openings are formed on the insulating protecting layer for the electrical connection pads to be exposed through. The conductive components such as the solder balls are formed in the openings of the insulating protecting layer
Data Source
AI summary
A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.