Embedded Semiconductor Substrate with Multi-Layered Conductive Structures
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Solution Overview
Problem
Current semiconductor substrates occupy excessive space due to separate packaging, board manufacturing, and assembly processes, and lack the flexibility to incorporate multiple redistribution layers (RDLs) within a compact size.
Innovation Solution
A semiconductor substrate with a multi-layered structure incorporating embedded components and conductive vias, where patterned conductive layers are embedded within dielectric layers, allowing for reduced substrate size and increased flexibility in circuit design, with the option to include more RDLs, and enabling double-sided interconnection for efficient electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate packaging, board manufacturing, and assembly processes are used, then each process can be performed independently with standard procedures, but the total space occupied on the substrate increases and manufacturing complexity increases
Solution Approach 1:
The patent combines packaging, board manufacturing, and assembly processes into a single integrated substrate structure. The semiconductor device is embedded directly within the substrate during manufacturing, eliminating the need for separate packaging and assembly steps. This merging of processes reduces the total space occupied on the substrate while maintaining manufacturing feasibility through coordinated process integration.
Solution Approach 2:
The patent transitions from a planar, surface-mounted arrangement to a three-dimensional embedded structure. By placing the semiconductor device within the substrate volume rather than on the surface, the design utilizes the vertical dimension to reduce the footprint area occupied on the substrate, thereby resolving the space constraint.
2Ease of manufacture
If traditional packaging and assembly processes are used, then standard manufacturing procedures can be followed, but the number of manufacturing steps increases and production time increases
Solution Approach 1:
The patent merges multiple discrete manufacturing processes (packaging, board manufacturing, assembly) into a single integrated manufacturing flow. The semiconductor device is embedded within the substrate during the board manufacturing process itself, eliminating sequential steps and reducing overall production time while maintaining standardized manufacturing procedures through coordinated process integration.
Solution Approach 2:
The semiconductor device is prepared and positioned within the substrate during the board manufacturing process before final assembly. This preliminary embedding action eliminates subsequent assembly steps, reducing the total number of manufacturing operations required and accelerating production throughput.
3Adaptability or versatility
If more circuit layers are added to increase functionality, then the substrate can support more RDLs, but the substrate size increases
Solution Approach 1:
The patent enables multiple RDLs to be stacked vertically within the embedded component structure rather than expanding horizontally across the substrate surface. By utilizing the vertical dimension within the component volume, the design accommodates additional circuit layers without increasing the substrate footprint, thereby maintaining compact size while enhancing functionality.
Solution Approach 2:
The patent implements a nested structure where multiple RDLs are contained within the embedded component volume. The component acts as a container that houses multiple conductive layers and dielectric structures, allowing dense integration of circuit functionality within a compact three-dimensional space without expanding the substrate area.
Data Source
AI summary
A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers. At least one of the patterned conductive layers is located at a depth spanning between a top surface of the passive layer and a bottom surface of the component