Embedded SiGe Source/Drain for SOI Floating Body Reduction

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Solution Overview

Problem

The floating body effect in silicon-on-insulator (SOI) transistors leads to variations in device performance, including threshold voltage reduction, kink in output characteristics, and dynamic issues like hysteresis and harmonic distortion, which are challenging to manage effectively with existing solutions.

Innovation Solution

The method involves forming a gate stack on a silicon-on-insulator substrate, creating trenches for epitaxial growth of silicon germanium in source and drain regions, and applying an amorphizing implant to reduce stress and proximity of SiGe to the device channel, thereby minimizing floating body effects and improving mobility and drive current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If body ties are placed on every NFET to reduce floating body effects, then floating body effects are reduced, but layout area consumption increases considerably

Engineering Contradiction:
Improvefloating body effect reductionVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent divides the source/drain regions into multiple segments by forming trenches within them and filling with SiGe material. This segmentation creates multiple SiGe bodies that collectively reduce the floating body effect across the entire transistor, replacing the need for individual body ties on each NFET and thereby reducing layout area consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces SiGe material as an intermediary substance within the source/drain regions. This SiGe material acts as a mediator that provides the electrical connection and potential equalization function previously achieved by body ties, while occupying less space and integrating seamlessly into the source/drain structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If SiGe is embedded in source/drain regions to reduce floating body effects, then device performance improves, but stress and proximity to channel may degrade mobility

Engineering Contradiction:
Improvefloating body effect reductionVSAvoidstress and proximity effect
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by forming trenches at specific locations within the source/drain regions and filling only those areas with SiGe material. This localized approach ensures that SiGe is positioned optimally to reduce floating body effects while maintaining adequate distance from the channel to minimize stress-induced mobility degradation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical and chemical parameters of the source/drain regions by embedding SiGe material with specific crystal structure and lattice constant. This parameter change enables the source/drain regions to provide both electrical connection for floating body effect reduction and controlled stress management to preserve carrier mobility.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces floating body effects and variability, enhancing channel mobility and drive current by minimizing the impact of stress and proximity of SiGe to the NFET device channel, while maintaining the benefits of embedded SiGe source/drain regions.

Implementation Method 1

Silicon germanium is epitaxially grown within the first trench and the second trench

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

An amorphizing species is implanted within the silicon germanium grown in the first trench and the silicon germanium grown in the second trench

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS8597991B2Embedded silicon germanium n-type filed effect transistor for reduced floating body effect
Publication Date: 2013.12.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8597991B2 patent drawing
  • US8597991B2 patent drawing
  • US8597991B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.