Embedded Silicon Substrate Fan-Out 3D Packaging
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Solution Overview
Problem
Current fan-out packaging technologies face challenges with molding compound wafers, including warpage, thermal expansion coefficient mismatches, and inadequate heat dissipation, which complicate high-density interconnection and miniaturization.
Innovation Solution
The use of a silicon substrate with embedded functional chips and polymer bonding, along with vertical conductive through holes for 3D interconnection, addresses these issues by providing a reliable and high-density packaging solution with matching thermal expansion coefficients and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If molding compound is used to reconstruct the wafer for fan-out packaging, then the package surface can be filled with I/Os through rewiring plane array, but warpage and thermal expansion coefficient mismatch occur causing reliability problems
Solution Approach 1:
The patent changes the material parameter from molding compound to silicon substrate, which fundamentally alters the thermal expansion coefficient to match the chip, eliminating thermal expansion mismatch and warpage issues while maintaining the fan-out packaging functionality
Solution Approach 2:
The patent uses a composite structure combining silicon substrate with polymer material for sealing, where the silicon substrate provides thermal stability and mechanical strength, while the polymer provides sealing and flexibility, achieving both reliability and packaging functionality
2Ease of manufacture
If molding compound is used to reconstruct the wafer, then fan-out structure can be formed, but heat dissipation becomes inadequate for high power consumption chips
Solution Approach 1:
The patent changes the substrate material from molding compound to silicon, which has superior thermal conductivity, thereby improving heat dissipation capability while maintaining the fan-out structure formation ability through established semiconductor manufacturing processes
3Adaptability or versatility
If molding compound wafer is used, then fan-out packaging can be achieved, but processing complexity increases due to warpage and fine line preparation difficulties
Solution Approach 1:
The patent changes the substrate material parameter to silicon, which has excellent mechanical stability and flatness, eliminating warpage issues and enabling standard photolithography and fine line processing without requiring specialized equipment or complex process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable 3D packaging with high-density interconnections, miniaturization, and thinness, overcoming the limitations of molding compound-based fan-out structures.
Implementation Method 1
the at least one functional chip is bonded with the at least one groove through a polymer
Implementation Method 2
the polymer material is photosensitive, and the polymer on pads on the at least one functional chip is opened
Implementation Method 3
at least one conductive through hole penetrating the silicon substrate and electrically connected to the pads is formed on the silicon substrate
Data Source
AI summary
An embedded silicon substrate fan-out type 3D packaging structure, comprising: a silicon substrate; and at least one functional chip, wherein the silicon substrate includes at least one groove, the at least one functional chip is embedded in the at least one groove with a pad surface facing upward, the at least one functional chip is bonded with the at least one groove through a polymer; a front surface of the silicon substrate, the pad surface of the at least one functional chip, and at least one gap between the at least one chip and the at least one groove are covered with a polymer material, and the polymer on pads on the at least one functional chip is opened; at least one conductive through hole is formed on the silicon substrate; and the silicon substrate further includes electrical interconnect structures, a first metal re-wiring and a second metal re-wiring.