Embedded Source Lines in Memory Cell Interconnection
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Solution Overview
Problem
Current resistive random access memory (RAM) technologies face challenges in further reducing the size of memory cells due to the need for additional circuits, even when the RAM is scaled down to nanometer sizes.
Innovation Solution
A memory device and manufacturing method that includes a substrate with a memory cell array and interconnection structure, where the memory cell interconnection structure features a dielectric layer and source lines embedded within it, directly contacting the source regions of transistor units, eliminating the need for conductive plugs and reducing the overall size of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If additional circuits are added to resistive RAM to maintain functionality, then the memory cell size cannot be reduced further
Solution Approach 1:
The invention extracts and eliminates the conductive plug component from the memory cell structure. By having source lines directly contact source regions without intermediate conductive plugs, the patent removes unnecessary structural elements, thereby reducing memory cell size while maintaining electrical functionality.
Solution Approach 2:
The invention merges the source line connection structure with the dielectric layer by embedding source lines directly into the dielectric layer. This integration eliminates the need for separate conductive plug structures, simplifying the overall device architecture and reducing the number of manufacturing steps.
2Ease of manufacture
If conductive plugs are used to connect source lines to source regions, then manufacturing complexity increases
Solution Approach 1:
The invention extracts and eliminates the conductive plug component from the memory cell structure. By having source lines directly contact source regions without intermediate conductive plugs, the patent removes unnecessary structural elements, thereby reducing memory cell size while maintaining electrical functionality.
Solution Approach 2:
The invention merges the source line connection structure with the dielectric layer by embedding source lines directly into the dielectric layer. This integration eliminates the need for separate conductive plug structures, simplifying the overall device architecture and reducing the number of manufacturing steps.
Data Source
AI summary
A memory device and a method of manufacturing the same are provided. The memory device includes a substrate, a memory cell array, and a memory cell interconnection structure. The memory cell array is disposed on the substrate and includes a plurality of memory cells. Each of the plurality of memory cells includes a transistor unit and a memory unit that are electrically connected to each other. The memory cell interconnection structure is disposed on the substrate, and is configured to establish an electrical connection between the plurality of memory cells. A plurality of source lines are embedded in a dielectric layer that directly covers the substrate. Each of the plurality of source lines is disposed on the substrate, and comes in direct contact with a source region of a corresponding one of the transistor units.