Embedded Split-Gate Flash Memory CMP Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of embedded split-gate flash memory devices faces challenges with CMP non-uniformity and etch defects due to differences in pattern density between the logic and flash memory regions, leading to yield losses.
Innovation Solution
A method involving selective etching and deposition processes to form a nitride layer, followed by chemical mechanical planarization of the floating gate polysilicon, and subsequent formation of control gates and floating gates, ensuring uniformity and reducing cone defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP is performed on floating gate polysilicon after STI formation, then the floating gate polysilicon is planarized, but CMP uniformity cannot be achieved due to pattern density differences between logic region and flash memory region
Solution Approach 1:
The patent applies different process treatments to different regions: the logic region retains its nitride layer while the flash memory region has the nitride layer removed. This local differentiation allows the logic region to maintain uniform CMP characteristics while the flash memory region can be selectively etched, resolving the CMP uniformity issue caused by pattern density differences between regions.
Solution Approach 2:
The patent segments the semiconductor substrate into two distinct processing zones: logic region and flash memory region. By selectively removing the nitride layer only in the flash memory region, the patent creates region-specific structures that enable uniform CMP processing across the entire substrate despite the underlying pattern density differences.
2Ease of manufacture
If etch processes are performed after non-uniform CMP, then control gate and floating gate are formed, but numerous cone defects are generated due to non-uniform floating gate polysilicon thickness
Solution Approach 1:
The patent performs preliminary selective etching of the nitride layer in the flash memory region before depositing the floating gate polysilicon. This preliminary action creates a uniform starting surface that prevents the formation of cone defects during subsequent etching processes, as the floating gate polysilicon can be deposited uniformly without encountering pre-existing thickness variations.
3Ease of manufacture
If floating gate polysilicon is deposited after STI formation, then the floating gate is formed, but the polysilicon thickness becomes non-uniform between logic region and flash memory region
Solution Approach 1:
The patent creates local quality differences by selectively removing the nitride layer only in the flash memory region while preserving it in the logic region. This selective removal creates region-specific surface characteristics that enable uniform floating gate polysilicon deposition across the entire substrate, as each region has optimized surface properties for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances CMP uniformity and reduces etch defects, improving the manufacturing yield and quality of embedded split-gate flash memory devices by simplifying the process and minimizing cone defects.
Implementation Method 1
removing the first nitride disposed in the flash memory region; The first nitride disposed in the flash memory region may be removed using a selective etchant
Implementation Method 2
performing chemical mechanical planarization on the floating gate polysilicon material
Implementation Method 3
depositing a floating gate polysilicon material over the semiconductor substrate
Data Source
AI summary
A method of manufacturing an embedded split-gate flash memory device is provided. The method includes: performing shallow trench isolation and chemical mechanical planarization on a semiconductor substrate comprising a flash memory region and a logic region, wherein a first oxide is formed on the semiconductor substrate and a first nitride is formed on the first oxide; forming a first photoresist over the logic region, and removing the first nitride disposed in the flash memory region; removing the first photoresist, and depositing a floating gate polysilicon material over the semiconductor substrate; performing chemical mechanical planarization on the floating gate polysilicon material; forming a control gate in the flash memory region; etching the floating gate polysilicon material to form a floating gate; forming a second photoresist over the flash memory region, and removing the first oxide and the first nitride disposed in the logic region; and removing the second photoresist.