Embedded Storage Fin Structure for Single-Chip Logic Integration
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while simplifying the complex packaging process, which is essential for reducing fabrication costs.
Innovation Solution
A semiconductor device design featuring a substrate with fins, gate structures, source/drain regions, and storage structures, including a dielectric layer and conductive layers, allows for a compact integration of transistors in a single chip, simplifying packaging and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase computing ability, then device density and computing power are improved, but manufacturing complexity and fabrication cost increase
Solution Approach 1:
The patent merges the DRAM storage structure and the transistor logic structure into a single integrated device. The shared fin, gate structure, and source/drain regions eliminate the need for separate packaging of storage and logic components, thereby reducing packaging complexity while maintaining high device density for improved computing ability
Solution Approach 2:
The fin and gate structure serve dual functions: they form the channel for transistor operation (logic function) and simultaneously provide the storage node for DRAM operation (storage function). This multi-functionality reduces the number of separate components needed, simplifying the overall device architecture and packaging process
2Productivity
If semiconductor devices are scaled down, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into distinct functional regions (channel region, first source/drain region, second source/drain region) with clearly defined interfaces. The gate structure is segmented to selectively control different regions, allowing for modular fabrication processes that can maintain precision even at scaled dimensions
Solution Approach 2:
Different regions of the device have optimized local properties: the channel region has specific doping characteristics for transistor control, while the storage node region has different doping for charge storage. This local optimization allows each region to be fabricated with precision tailored to its specific function, improving overall manufacturing feasibility at scaled dimensions
3Productivity
If semiconductor devices are scaled down, then device density is improved, but fabrication cost increases
Solution Approach 1:
By combining storage and logic functions in a single device structure, the patent eliminates the need for separate fabrication and packaging processes for discrete storage and logic components. This merging reduces the total number of manufacturing steps, lowering fabrication cost while achieving high device density through vertical integration
Solution Approach 2:
The patent transitions from planar device architecture to vertical three-dimensional architecture with fins extending in the vertical dimension. This dimensional change increases device density without proportionally increasing fabrication complexity, as the vertical structures can be formed using standard semiconductor fabrication techniques adapted for 3D geometries
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a fin positioned on the substrate, a gate structure positioned on the fin, a pair of source/drain regions positioned on two sides of the fin, a dielectric layer positioned above the drain region and adjacent to the gate structure, and a storage conductive layer positioned on the dielectric layer. The drain region, the dielectric layer and the storage conductive layer form a storage structure.