Embedded Substrate Guide Holes for Via Alignment
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Solution Overview
Problem
As electronic components miniaturize, the existing methods for forming via holes in embedded substrates face challenges in achieving precise electrical connectivity due to increased placing tolerance and via hole processing errors, leading to reduced contact area and stability issues.
Innovation Solution
The proposed electronic component embedded substrate includes a first insulating layer with a cavity and a first metal pattern featuring guide holes to expose external electrodes, allowing for precise via hole formation using CO2 laser processing, which self-aligns with the electrodes and enhances connectivity, along with additional layers and vias for improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of electronic component is reduced, then miniaturization is achieved, but matching error of via and electronic component increases
Solution Approach 1:
The patent divides the via structure into multiple segments: a first via portion extending from the first surface to expose the external electrode, and a second via portion extending from the first surface to expose the circuit pattern. This segmentation allows each via portion to be independently optimized for its specific function, improving overall alignment precision despite smaller component sizes.
Solution Approach 2:
The patent introduces a vertical dimension to the via alignment solution by creating staggered via portions at different depths. The first via portion targets the external electrode while the second via portion targets the circuit pattern, utilizing the third dimension (depth) to resolve horizontal alignment mismatches that occur with miniaturized components.
2Volume of moving object
If via hole size is reduced, then smaller electronic components can be accommodated, but electrical connectivity deteriorates
Solution Approach 1:
The electrical connection path is segmented into multiple via portions rather than relying on a single via hole. The first via portion provides connection to the external electrode while the second via portion connects to the circuit pattern, distributing the connectivity function across multiple structures to maintain reliability despite reduced individual via sizes.
Solution Approach 2:
The patent merges multiple via functions into a unified via structure system. The first and second via portions are integrated within the same via hole formation process, combining their functions to achieve both small size accommodation and reliable electrical connectivity through cooperative operation of the segmented via portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable and precise electrical connectivity even with smaller electronic components, overcoming the limitations of conventional methods by ensuring accurate via hole formation and increased contact area, thus maintaining connectivity despite reduced component sizes.
Implementation Method 1
allowing for precise via hole formation using CO2 laser processing
Data Source
AI summary
The present invention relates to an electronic component embedded substrate including: a first insulating layer including a cavity; an electronic component inserted in the cavity; a first metal pattern formed on a lower surface of the first insulating layer to mount the electronic component thereon and including at least one guide hole for exposing a portion of the external electrode; a second insulating layer formed on the lower surface of the first insulating layer to cover the first metal pattern; a first circuit pattern formed on a lower surface of the second insulating layer; and a first via for electrically connecting the first external electrode exposed through the guide hole and the first circuit pattern, and can improve electrical connectivity between the external electrode and the via even when the size of the external electrode of the electronic component is reduced than before.