Embedded Switches in Memory Arrays to Reduce Capacitive Loading
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Solution Overview
Problem
Existing memory devices face challenges with high bit line and select line capacitance, which affect operating speed and power consumption, particularly in three-dimensional memory arrays.
Innovation Solution
Incorporation of switches to selectively couple or decouple local lines to global lines in memory systems, reducing capacitive loading by configuring subsets of memory cells for access, thereby improving operating speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory arrays are used to increase storage density, then memory capacity is improved, but bit line and select line capacitance increases causing slower operating speed
Solution Approach 1:
The memory array is divided into multiple blocks, with each block containing a subset of memory cells. Switches are used to selectively couple only the required block to the bit line and select line, segmenting the total capacitive load into smaller manageable portions. This allows high-density 3D memory architecture while maintaining faster access speeds by accessing only relevant blocks.
2Quantity of substance
If three-dimensional memory arrays are used to increase storage density, then memory capacity is improved, but bit line and select line capacitance increases causing higher power consumption
Solution Approach 1:
The memory array is divided into multiple blocks, with each block containing a subset of memory cells. Switches are used to selectively couple only the required block to the bit line and select line, segmenting the total capacitive load into smaller manageable portions. This allows high-density 3D memory architecture while maintaining faster access speeds by accessing only relevant blocks.
Solution Approach 2:
Instead of coupling all memory cells to the bit line and select line simultaneously, only a partial subset of blocks is coupled at any given time based on the access requirement. This partial action reduces the capacitive loading and associated power consumption while maintaining the ability to access any memory cell in the full 3D array when needed.
3Speed
If switches are added to reduce capacitive loading, then operating speed is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple blocks, with each block containing a subset of memory cells. Switches are used to selectively couple only the required block to the bit line and select line, segmenting the total capacitive load into smaller manageable portions. This allows high-density 3D memory architecture while maintaining faster access speeds by accessing only relevant blocks.
Solution Approach 2:
The switches are integrated within the memory array structure itself, using the same transistor technology and fabrication processes as the memory cells. This self-service approach allows the switching functionality to be implemented without adding significant external complexity, as the switches are formed using standard memory fabrication techniques.
Data Source
AI summary
One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.