Embedded Through-Via Interposer for Packaging Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional packaging substrates with low-k dielectric materials face issues such as cracking due to thermal stress mismatch with semiconductor chips and mismatched pitches between micro-scale flip-chip bonding pads and high-density nano-scale circuits, leading to reduced reliability and compatibility.
Innovation Solution
A packaging substrate with an embedded through-via interposer, featuring conductive through-vias and a redistribution layer, which electrically connects to both the semiconductor chip and a built-up structure, allowing for better pitch matching and reduced thermal stress, thereby improving reliability and compatibility without altering existing IC supply chains or infrastructures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If low-k dielectric material is used in BEOL to improve electrical performance, then signal transmission quality is improved, but thermal stress mismatch causes cracking and reduces reliability
Solution Approach 1:
An interposer structure is introduced as an intermediary component between the packaging substrate and the semiconductor chip. The interposer includes a first substrate with conductive through-vias and a second substrate with circuit layers, serving as a buffer that matches thermal expansion coefficients and reduces stress transmission to the low-k dielectric material during thermal cycling.
Solution Approach 2:
The packaging structure employs composite material design by combining different substrate materials with complementary properties. The first substrate uses materials optimized for electrical performance while the second substrate provides mechanical stability and thermal matching, creating a composite system that balances electrical performance and thermal stress resistance.
2Ease of manufacture
If micro-scale flip-chip bonding pads are used on packaging substrate, then manufacturing is simplified, but pitch mismatch occurs with high-density nano-scale circuits
Solution Approach 1:
The interposer structure utilizes vertical layering to resolve the pitch mismatch problem. By stacking multiple substrates with conductive through-vias connecting different layers, the system achieves fine pitch routing in the vertical dimension while maintaining compatibility with standard micro-scale bonding pads on the packaging substrate.
Solution Approach 2:
The interposer is segmented into multiple functional layers: a first substrate containing conductive through-vias for fine-pitch connections, and a second substrate with circuit layers for signal routing. This segmentation allows each layer to be optimized independently for its specific function while working together to bridge the pitch gap.
Data Source
AI summary
A method of fabricating a packaging substrate having an embedded through-via interposer is provided. The method includes providing a through-via interposer having opposite first and second sides and conductive through-vias in communication with the first and second sides, wherein each of the conductive through-vias has a first end surface on the first side and a second end surface on the second side, and the second end surfaces protrude below the second side to serve as conductive bumps. Next, forming a redistribution layer on the first side and the first end surfaces such that the redistribution layer electrically connects with the first end surfaces. Afterwards, forming an encapsulant layer to encapsulate and embed the through-via interposer, wherein the encapsulant layer has opposite first and second surfaces. Next, forming a built-up structure on the second surface of the encapsulant layer, the second side of the through-via interposer and the conductive bumps.