Embedded Trace Substrate for System in Package Integration
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Solution Overview
Problem
Existing system in package (SIP) technologies face challenges in integrating silicon dies and passive components efficiently, particularly in achieving smaller size, lower cost, and better performance for wearable and IoT devices, with traditional methods struggling to optimize electrical and thermal performance.
Innovation Solution
The integration of a silicon die and passive components using an embedded trace substrate with redistribution layers, where the silicon die is mounted on one side and passive components on the other, connected through copper pillars and molding compounds, with solder balls providing output, enabling efficient signal communication and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional SIP technologies are used to integrate silicon die and passive components, then device functionality is achieved, but device size becomes larger and manufacturing cost increases
Solution Approach 1:
The patent combines silicon die and passive components into a single integrated package structure, where both components are mounted on opposite sides of an embedded trace substrate and encapsulated together. This merging approach eliminates the need for separate packaging, reducing overall device volume while maintaining functionality.
Solution Approach 2:
The patent utilizes the z-dimension (vertical stacking) by placing silicon die on one side of the embedded trace substrate and passive components on the opposite side, connected through through-substrate vias. This three-dimensional integration approach significantly reduces the footprint area compared to planar arrangements.
2Reliability
If traditional packaging methods are used, then components are protected, but signal transmission distance increases and electrical performance deteriorates
Solution Approach 1:
The patent extracts the interconnection function from traditional long external traces by implementing embedded traces within the substrate and through-substrate vias. This creates direct, short electrical pathways between silicon die and passive components, minimizing signal line length and improving electrical performance.
3Temperature
If conventional SIP structures are used, then components are assembled, but thermal dissipation efficiency is reduced due to longer heat paths
Solution Approach 1:
The patent merges the thermal management function into the package structure by using the embedded trace substrate and molding compound as heat dissipation pathways. The copper traces and vias act as thermal conduction paths, directly conducting heat from the silicon die to the package exterior, significantly reducing heat path length.
4Ease of manufacture
If multiple separate packaging processes are used, then components are individually protected, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent merges multiple packaging processes into a single integrated manufacturing flow. The embedded trace substrate is prepared once, then both silicon die and passive components are mounted and encapsulated in one molding process, eliminating the need for separate packaging operations and reducing manufacturing cost.
Solution Approach 2:
The embedded trace substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection through traces and vias, thermal management pathways, and structural framework for mounting both active and passive components. This multi-functionality reduces the number of separate components and processes needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller, cost-effective SIP with improved electrical performance and heat dissipation due to shorter signal lines and better copper trace thickness, reducing manufacturing complexity and costs while enhancing yield and revenue.
Implementation Method 1
electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers
Implementation Method 2
improved electrical performance and heat dissipation due to shorter signal lines and better copper trace thickness
Data Source
AI summary
A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.