Embedded Vertical Interconnects in PoP Packaging
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Solution Overview
Problem
Current 3-D packaging technologies, such as package-on-package (PoP), require costly laser drilling for interconnect structures, leading to increased equipment costs, longer cycle times, and yield losses due to uncontrollable vertical interconnections and contamination risks during semiconductor device manufacturing.
Innovation Solution
The use of Printed Wiring Board (PWB) modular units with embedded vertical interconnect structures, which provide cost-effective and controlled vertical interconnections by replacing traditional laser drilling, thereby reducing manufacturing complexity and contamination risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser drilling is used to form vertical interconnect structures in PoP packaging, then interconnect structures can be formed, but equipment costs increase and manufacturing complexity increases
Solution Approach 1:
The patent replaces the laser drilling process (thermal/optical system) with a mechanical embossing process. The embossing process uses a stamp or mold to physically form the vertical interconnect structures through the encapsulant material, eliminating the need for expensive laser drilling equipment while achieving the same interconnect formation function.
2Reliability
If laser drilling is used to form vertical interconnect structures, then interconnections can be created, but cycle time increases and productivity decreases
Solution Approach 1:
The patent performs the vertical interconnect structure formation as a preliminary action during the encapsulant application process itself. By embossing the interconnect structures while the encapsulant is being applied or immediately after, the process eliminates the need for separate, time-consuming laser drilling steps, thereby reducing cycle time and increasing manufacturing throughput.
3Reliability
If laser drilling is used for vertical interconnections, then interconnect structures can be formed, but contamination risks increase due to unprotected contacts
Solution Approach 1:
The patent provides beforehand protection by forming the vertical interconnect structures within the encapsulant material itself, which acts as a protective cushion or barrier. The encapsulant covers and protects the contacts from the beginning, preventing contamination before it can occur, rather than requiring additional protective measures after contact formation.
4Ease of manufacture
If traditional PoP packaging is used, then semiconductor devices can be packaged, but conductive materials can be transferred to semiconductor die causing contamination
Solution Approach 1:
The patent introduces the encapsulant material as an intermediary barrier between the conductive vertical interconnect structures and the semiconductor die. This intermediary layer prevents direct contact and potential transfer of conductive materials to the die, eliminating contamination risks while still allowing the package formation process to proceed.
Data Source
AI summary
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.