Embedded Wiring Semiconductor Package Structure

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Solution Overview

Problem

Conventional semiconductor package structures, such as QFP and BGA, face limitations in I/O connections, profile thickness, signal transmission, fabricating complexity, delamination, and thermal expansion coefficient mismatch due to multi-layered carriers and complex wiring arrangements.

Innovation Solution

A single-layered semiconductor package structure with a wiring layer embedded in an insulative layer, where one side is coupled to electronic components and the other to soldering balls, reducing signal path length and interfaces, and using a single material for the insulative layer to prevent warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a multi-layered carrier with complex wiring arrangement is used, then the number of I/O connections can be increased, but the device complexity and fabrication difficulty increase

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidwiring arrangement complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the wiring function into separate segments: the carrier body provides mechanical support while discrete wiring layers are added independently. This allows I/O connections to be increased through additional wiring layers without complicating the base carrier structure, as each wiring layer can be fabricated and attached separately

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar wiring arrangements to three-dimensional stacked wiring layers. By adding wiring layers in the vertical dimension rather than expanding horizontally, the number of I/O connections increases while maintaining a compact footprint and avoiding increased carrier complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If a multi-layered carrier with conductive pillars is used, then high I/O connections can be achieved, but the profile thickness increases

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidprofile thickness

Core Design Contradiction:

Quantity of substanceVSLength of stationary object

Solution Approach 1:

The patent nests multiple wiring layers within a compact vertical stack, with each wiring layer containing I/O connections. This nesting approach allows high I/O connectivity while maintaining a low profile thickness, as the wiring layers are tightly integrated rather than stacked with large spacing

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent uses thin film wiring layers with flexible interconnections that can be bent and routed efficiently. This allows the wiring to achieve high I/O connections without requiring thick rigid structures, maintaining a low profile thickness through flexible thin-film construction

Inventive Principle:

Principle #30Flexible shells and thin films

3Quantity of substance

If multiple wiring layers and conductive pillars are fabricated, then high I/O connections are achieved, but the signal transmission path becomes too long

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidsignal transmission path length

Core Design Contradiction:

Quantity of substanceVSLength of moving object

Solution Approach 1:

The patent inverts the conventional approach by routing signals through the carrier body itself rather than through long external paths. The carrier is designed with embedded conductive pathways that provide direct signal transmission between wiring layers, shortening the signal path while maintaining high I/O connectivity

Inventive Principle:

Principle #13The other way round (Inversion)

4Quantity of substance

If a hybrid carrier with multiple layers of different materials is used, then high I/O connections can be achieved, but delamination and warpage increase

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoiddelamination resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent uses a carrier body made of a single homogeneous material with uniform thermal expansion properties. This homogeneity prevents internal stress and delamination that would occur with hybrid multi-material carriers, while still achieving high I/O connections through the stacked wiring layer architecture

Inventive Principle:

Principle #33Homogeneity

Solution Approach 2:

The patent introduces different materials locally at the wiring layer interfaces rather than throughout the entire carrier structure. The carrier body remains homogeneous, while localized adhesive or interface layers are added only where needed for wiring attachment, minimizing material mismatches and preventing warpage

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11417581B2Package structure

Publication Date: 2022.08.16 PHOENIX PIONEER TECH

AI summary

A semiconductor package is provided and includes: an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on the second side of the wiring layer and electrically connected to the wiring layer; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the insulative layer and encapsulating the electronic component. Therefore, the single wiring layer is allowed to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path.