Emerging Memory Bank Remapping for Defective-Bank Tolerance
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Solution Overview
Problem
State-of-the-art memory devices are rendered unusable if a single memory bank on a memory die becomes faulty, leading to reduced yield and inefficiency.
Innovation Solution
Implement a memory bank remapping process that updates the mapping between bank identifiers and physical memory banks, consolidating available banks in consecutive order, and generates new addresses using a mod division circuit for non-power-of-two bank configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory bank on a memory die is faulty or broken, then the entire memory die is unusable, but this leads to reduced yield and inefficiency
Solution Approach 1:
The memory die is divided into multiple independent memory banks that can be individually tested and identified. When a bank is defective, the system segments the operational memory banks from the defective one, allowing the good banks to be remapped and used independently, thus preventing total die rejection.
Solution Approach 2:
The patent changes the addressing parameters by introducing a remapping mechanism that reassigns bank identifiers to physical banks. This parameter transformation allows the system to map logical bank addresses to physical banks excluding defective ones, maintaining usability despite hardware defects.
2Speed
If memory banks are accessed in parallel, then data transfer rate is improved, but a single defective bank renders the entire die unusable
Solution Approach 1:
The memory bank mapping is made dynamic through the remapping mechanism. The system can adaptively reconfigure which physical banks are accessible based on defect detection, allowing parallel access to remain efficient while excluding defective banks from the parallel operation set.
Solution Approach 2:
A remapping mechanism acts as an intermediary between the address space and physical memory banks. This intermediary layer translates logical bank addresses to physical banks, filtering out defective banks while preserving the parallel access architecture for healthy banks.
3Quantity of substance
If the number of memory banks is increased to improve capacity, then more data can be stored, but the probability of having defective banks increases
Solution Approach 1:
The system performs preliminary testing of each memory bank during manufacturing to identify defective banks before the memory die is deployed. This advance detection allows for pre-configured remapping that excludes defective banks from operational use, ensuring reliability even as capacity increases.
Solution Approach 2:
The patent creates a virtual copy of the memory bank mapping through the remapping register array. This virtual mapping layer allows the system to present a complete address space to applications while physically accessing only the healthy banks, effectively copying the functionality of missing banks through software-based redirection.
Data Source
AI summary
A memory device includes a controller and an addressing system that enables the memory device to support memory components having one or more defective memory banks. During a testing phase of a memory component manufacturing process, memory components with defective memory banks are identified and a memory bank remapping process is initiated. During the remapping process, entries in a bank remapping register array are updated such that available physical memory banks are logically mapped in a consecutive order. Memory components having the same number of available memory banks are grouped and used in a memory device. If the number of available memory banks of each memory component is not a power of two, a mod division circuit is used to generate a memory component address for the memory component. The memory component address includes a bank identifier and an intra-bank address.