EMIB Patch FLI-on-Carrier Assembly for Microbump BTV Control
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Solution Overview
Problem
Current EMIB substrate bump thickness variation (BTV) requirements for first layer interconnect (FLI) are stringent due to small micro-bump pitching, leading to complex and costly manufacturing processes with non-uniform bump heights and increased processing steps.
Innovation Solution
The FLI is created first on a smooth glass carrier, allowing precise control of solder volume and reducing BTV variations by flipping the bridge die for connections, eliminating the need for subsequent lithography steps and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional EMIB substrate manufacturing process is used with small micro-bump pitching, then I/O density requirements are met, but bump thickness variation becomes difficult to control and manufacturing complexity increases
Solution Approach 1:
The first layer interconnect (FLI) is formed on the carrier substrate before the bridge die is attached. This preliminary formation of the FLI with controlled solder volume establishes a uniform base layer that enables precise bump thickness control when micro-bumps are subsequently formed, resolving the contradiction between high I/O density and bump thickness variation control
Solution Approach 2:
A carrier substrate is introduced as an intermediary platform to support the FLI formation process. The carrier provides a stable, flat surface that enables precise control of solder volume and bump geometry, acting as a mediator between the manufacturing process and the final micro-bump structure to achieve both high density and precise thickness control
2Reliability
If traditional EMIB manufacturing process with multiple lithography steps is used, then connections are established, but processing steps increase and manufacturing complexity increases
Solution Approach 1:
The FLI is formed in advance on the carrier substrate before bridge die attachment. This preliminary action establishes the interconnect structure beforehand, eliminating the need for subsequent lithography steps that would otherwise be required to create connections after die attachment, thereby reducing processing steps while maintaining connection reliability
Solution Approach 2:
The conventional sequence is inverted: instead of forming interconnects after die attachment through lithography, the FLI is formed first on the carrier, then the bridge die is attached to the already-formed interconnect structure. This inversion eliminates multiple lithography steps and reduces manufacturing complexity while ensuring reliable connections
Data Source
AI summary
A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.